From efb0a8bf11e8b5b093699f3b3a639f7d4c130aec Mon Sep 17 00:00:00 2001 From: Andre Heinemans Date: Thu, 11 Dec 2025 10:30:30 +0100 Subject: [PATCH 1/4] app: b3rb: add mr_navq95b board Co-authored-by: Peter van der Perk Signed-off-by: Andre Heinemans --- app/b3rb/CMakeLists.txt | 5 +- ...tcm_linker.ld => mr_navq95_itcm_linker.ld} | 0 app/b3rb/boards/mr_navq95b_m7_flash.conf | 116 ++++++++++ app/b3rb/boards/mr_navq95b_m7_flash.overlay | 215 ++++++++++++++++++ 4 files changed, 334 insertions(+), 2 deletions(-) rename app/b3rb/boards/{mr_navq95a_itcm_linker.ld => mr_navq95_itcm_linker.ld} (100%) create mode 100644 app/b3rb/boards/mr_navq95b_m7_flash.conf create mode 100644 app/b3rb/boards/mr_navq95b_m7_flash.overlay diff --git a/app/b3rb/CMakeLists.txt b/app/b3rb/CMakeLists.txt index 7713e30b..3f4c3999 100644 --- a/app/b3rb/CMakeLists.txt +++ b/app/b3rb/CMakeLists.txt @@ -113,9 +113,10 @@ target_sources(app PRIVATE ${SOURCE_FILES}) target_include_directories(app SYSTEM BEFORE PRIVATE ${ZEPHYR_BASE}/include ${CMAKE_BINARY_DIR}) -if(CONFIG_BOARD STREQUAL "mr_navq95a") +if ((CONFIG_BOARD STREQUAL "mr_navq95a") OR + (CONFIG_BOARD STREQUAL "mr_navq95b")) # Relocate code to ITCM - zephyr_linker_sources(ITCM_SECTION boards/mr_navq95a_itcm_linker.ld) + zephyr_linker_sources(ITCM_SECTION boards/mr_navq95_itcm_linker.ld) zephyr_code_relocate(LIBRARY nanopb LOCATION ITCM_TEXT) # Relocate log ring buffer to SDRAM zephyr_linker_sources(SECTIONS boards/navq95.ld) diff --git a/app/b3rb/boards/mr_navq95a_itcm_linker.ld b/app/b3rb/boards/mr_navq95_itcm_linker.ld similarity index 100% rename from app/b3rb/boards/mr_navq95a_itcm_linker.ld rename to app/b3rb/boards/mr_navq95_itcm_linker.ld diff --git a/app/b3rb/boards/mr_navq95b_m7_flash.conf b/app/b3rb/boards/mr_navq95b_m7_flash.conf new file mode 100644 index 00000000..0d45698f --- /dev/null +++ b/app/b3rb/boards/mr_navq95b_m7_flash.conf @@ -0,0 +1,116 @@ +CONFIG_ENTROPY_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_SPEED_OPTIMIZATIONS=n +CONFIG_SIZE_OPTIMIZATIONS=n +CONFIG_DEBUG_OPTIMIZATIONS=y +CONFIG_CODE_DATA_RELOCATION=y + +CONFIG_DISK_ACCESS=n +CONFIG_FS_FATFS_EXFAT=n +CONFIG_DISK_DRIVER_SDMMC=n +CONFIG_FS_FATFS_MOUNT_MKFS=n +CONFIG_CEREBRI_SYNAPSE_LOG_SDCARD=y +CONFIG_RING_BUFFER_LARGE=y + +CONFIG_TEST=y +CONFIG_UBSAN=n +CONFIG_ASSERT=y +CONFIG_ASSERT_LEVEL=2 +CONFIG_ASSERT_VERBOSE=y + +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 + +CONFIG_STACK_CANARIES=y + +CONFIG_ISR_STACK_SIZE=2048 + +CONFIG_SHELL_STACK_SIZE=4096 + +CONFIG_LOG_MODE_DEFERRED=y +CONFIG_LOG_MODE_IMMEDIATE=n + +CONFIG_FPU=y + +# config +CONFIG_INPUT=y +# CONFIG_INPUT_GPIO_KEYS=y (not in dt) +CONFIG_INPUT_SBUS=y +CONFIG_INPUT_SBUS_THREAD_STACK_SIZE=1024 +CONFIG_INPUT_SBUS_REPORT_FILTER=0 +CONFIG_INPUT_EVENT_DUMP=n +CONFIG_INPUT_SHELL=n +CONFIG_INPUT_MODE_SYNCHRONOUS=y + + +CONFIG_ZROS_SENSE_IMU=y +#CONFIG_ZROS_SENSE_MAG=y +CONFIG_CEREBRI_SENSE_SAFETY=n + +# I3C tends to lock up the system, needs a driver fix +CONFIG_ZROS_SENSE_MAG=n +CONFIG_I3C=n +CONFIG_BMM350=n +CONFIG_BMP581=n + +CONFIG_CEREBRI_SYNAPSE_ETH_RX=y +CONFIG_CEREBRI_SYNAPSE_ETH_TX=y + +CONFIG_PWM=y +CONFIG_CEREBRI_ACTUATE_PWM=y +CONFIG_CEREBRI_ACTUATE_PWM_SHELL=n + +CONFIG_LED_STRIP=n +CONFIG_APA102_STRIP=n +CONFIG_CEREBRI_ACTUATE_LED_ARRAY=n +CONFIG_CEREBRI_SENSE_POWER=y +CONFIG_CEREBRI_ACTUATE_SOUND=n + +CONFIG_CAN=y +CONFIG_CAN_MAX_FILTER=5 +CONFIG_CAN_SHELL=y + +CONFIG_NET_DRIVERS=y + +CONFIG_NET_SOCKETS_CAN=y +CONFIG_NET_DEFAULT_IF_CANBUS_RAW=y + +CONFIG_CAN_LOG_LEVEL_DBG=n +CONFIG_CAN_FD_MODE=y +CONFIG_SHELL_ARGC_MAX=72 +CONFIG_I2C=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=y +CONFIG_HEAP_MEM_POOL_SIZE=16384 + +# Debugging +CONFIG_DEBUG_THREAD_INFO=y + +# Logging +#CONFIG_LOG_BACKEND_NET=n +#CONFIG_LOG_BACKEND_NET_SERVER="192.0.2.2" + +# RPMsg +CONFIG_IPM=y +CONFIG_IPM_MBOX=y +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_OPENAMP=y +CONFIG_OPENAMP_COPY_RSC_TABLE=y +CONFIG_OPENAMP_RSC_TABLE_NUM_RPMSG_BUFF=8 +CONFIG_OPENAMP_RSC_TABLE=y +CONFIG_OPENAMP_MASTER=n +CONFIG_OPENAMP_WITH_DCACHE=y +CONFIG_CEREBRI_SYNAPSE_RPMSG=y + +# TTY over RPMsg (uncomment block below to enable) +#CONFIG_SHELL_BACKEND_RPMSG=y +#CONFIG_SHELL_BACKEND_SERIAL=n +#CONFIG_ASSERT=n + +# Disable fat and enable rpmsgfs +CONFIG_FILE_SYSTEM_RPMSGFS=y +CONFIG_FAT_FILESYSTEM_ELM=n +CONFIG_FILE_SYSTEM_SHELL=y + +# Disable atomic 64 support otherwise open-amp cannot be linked +CONFIG_COMPILER_OPT="-DNO_ATOMIC_64_SUPPORT" diff --git a/app/b3rb/boards/mr_navq95b_m7_flash.overlay b/app/b3rb/boards/mr_navq95b_m7_flash.overlay new file mode 100644 index 00000000..16fcd7bf --- /dev/null +++ b/app/b3rb/boards/mr_navq95b_m7_flash.overlay @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2025 CogniPilot Foundation */ +#include +#include +#include +#include +#include + +/ { + pwm_actuators: pwm_actuators { + compatible = "cerebri,pwm-actuators"; + aux0 { + input-type = "position"; + input-index = <0>; + pwms = <&tpm5 1 PWM_HZ(50) PWM_POLARITY_NORMAL>; + disarmed = <1500>; + min = <1100>; + max = <1900>; + center = <1500>; + scale = <800>; + scale-div = <1>; + + }; + aux1 { + input-type = "velocity"; + input-index = <0>; + pwms = <&tpm3 1 PWM_HZ(20000) PWM_POLARITY_NORMAL>; + disarmed = <25000>; + min = <0>; + max = <50000>; + center = <25000>; + scale = <717>; + scale-div = <1>; + use-nano-seconds; + }; + aux2 { + input-type = "normalized"; + input-index = <0>; + pwms = <&tpm5 0 PWM_HZ(50) PWM_POLARITY_NORMAL>; + disarmed = <0>; + min = <0>; + max = <20000>; + center = <0>; + scale = <20000>; + scale-div = <1>; + }; + }; + + chosen { + /* zephyr,canbus = &flexcan5; */ + + zephyr,ipc_shm = &shmem; + zephyr,ipc_rsc_table = &rsc_table; + zephyr,ipc = &mailbox0; + }; + + ocram: memory@20480000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x20480000 DT_SIZE_K(256)>; + zephyr,memory-region = "OCRAM"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + ddr: ddr@90000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x90000000 DT_SIZE_M(4)>; + zephyr,memory-region = "DDR"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + shmem: memory@88000000 { + compatible = "mmio-sram"; + reg = <0x88000000 0x500000>; + }; + + rsc_table: memory@88220000 { + compatible = "mmio-sram"; + reg = <0x88220000 0x100>; + }; + + mailbox0: mailbox { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mu7 1>, <&mu7 1>; + mbox-names = "tx", "rx"; + status = "okay"; + }; + + aliases { + accel0 = &bmi08x_accel; + gyro0 = &bmi08x_gyro; + mag0 = &bmm350; + power0 = &ina230; + wheel-odometry0 = &tpm4; + rc = &sbus0; + /* can0 = &flexcan5; */ + }; +}; + +/* Reconfigure TPM4 as QDEC */ +&tpm4 { + compatible = "nxp,tpm-qdec"; + micro-ticks-per-rev = <685440000>; + /delete-property/ prescaler; +}; + +&tpm5 { + prescaler = <4>; +}; + +&lpi2c6 { + clock-frequency = ; + + ina230: ina230@40 { + compatible = "ti,ina230"; + reg = <0x40>; + current-lsb-microamps = <10000>; + rshunt-micro-ohms = <2000>; + }; +}; + +&lpuart5 { + status = "okay"; + current-speed = <100000>; + rx-invert; + + sbus0: sbus { + compatible = "futaba,sbus"; + chan_1 { + channel = <1>; + type = ; + zephyr,code = <1>; + }; + chan_2 { + channel = <2>; + type = ; + zephyr,code = <2>; + }; + chan_3 { + channel = <3>; + type = ; + zephyr,code = <3>; + }; + chan_4 { + channel = <4>; + type = ; + zephyr,code = <4>; + }; + chan_5 { + channel = <5>; + type = ; + zephyr,code = <5>; + }; + chan_6 { + channel = <6>; + type = ; + zephyr,code = <6>; + }; + chan_7 { + channel = <7>; + type = ; + zephyr,code = <7>; + }; + chan_8 { + channel = <8>; + type = ; + zephyr,code = <8>; + }; + chan_9 { + channel = <9>; + type = ; + zephyr,code = <9>; + }; + chan_10 { + channel = <10>; + type = ; + zephyr,code = <10>; + }; + chan_11 { + channel = <11>; + type = ; + zephyr,code = <11>; + }; + chan_12 { + channel = <12>; + type = ; + zephyr,code = <12>; + }; + chan_13 { + channel = <13>; + type = ; + zephyr,code = <13>; + }; + chan_14 { + channel = <14>; + type = ; + zephyr,code = <14>; + }; + chan_15 { + channel = <15>; + type = ; + zephyr,code = <15>; + }; + chan_16 { + channel = <16>; + type = ; + zephyr,code = <16>; + }; + }; +}; + +&mu7 { + status = "okay"; +}; From 7673a93840d518664ec7a1f183f4e90bc6a658aa Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Fri, 19 Dec 2025 10:22:23 +0100 Subject: [PATCH 2/4] dshot: imx95 fix bit timing Signed-off-by: Peter van der Perk --- drivers/zephyr/misc/nxp_flexio_dshot/nxp_flexio_dshot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/zephyr/misc/nxp_flexio_dshot/nxp_flexio_dshot.c b/drivers/zephyr/misc/nxp_flexio_dshot/nxp_flexio_dshot.c index 400b207c..096f132e 100644 --- a/drivers/zephyr/misc/nxp_flexio_dshot/nxp_flexio_dshot.c +++ b/drivers/zephyr/misc/nxp_flexio_dshot/nxp_flexio_dshot.c @@ -213,7 +213,7 @@ static int nxp_flexio_dshot_set_clock(const struct nxp_flexio_dshot_config *cfg) #endif #ifdef CONFIG_SOC_MIMX9596_M7 - uint64_t flexio_clk = 44444444; + uint64_t flexio_clk = 133333333; struct scmi_protocol *proto = cfg->clock_dev->data; struct scmi_clock_rate_config clk_cfg = {0}; ret = scmi_clock_parent_set(proto, IMX95_CLK_FLEXIO1, IMX95_CLK_SYSPLL1_PFD1_DIV2); From e59de5c28a61e0207de922c01c4fe20b571f1f9d Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Fri, 19 Dec 2025 10:22:43 +0100 Subject: [PATCH 3/4] rdd2: Add mr_navq95b support Signed-off-by: Peter van der Perk --- app/rdd2/CMakeLists.txt | 2 +- app/rdd2/boards/mr_navq95b_m7_flash.conf | 162 +++++++++++ app/rdd2/boards/mr_navq95b_m7_flash.overlay | 294 ++++++++++++++++++++ 3 files changed, 457 insertions(+), 1 deletion(-) create mode 100644 app/rdd2/boards/mr_navq95b_m7_flash.conf create mode 100644 app/rdd2/boards/mr_navq95b_m7_flash.overlay diff --git a/app/rdd2/CMakeLists.txt b/app/rdd2/CMakeLists.txt index 685534ec..dddf3573 100644 --- a/app/rdd2/CMakeLists.txt +++ b/app/rdd2/CMakeLists.txt @@ -156,7 +156,7 @@ if(CONFIG_BOARD STREQUAL "mr_vmu_tropic") zephyr_code_relocate(LIBRARY nanopb LOCATION ITCM_TEXT) endif() -if(CONFIG_BOARD STREQUAL "mr_navq95a") +if(CONFIG_BOARD STREQUAL "mr_navq95a" OR CONFIG_BOARD STREQUAL "mr_navq95b") # Relocate code to ITCM zephyr_linker_sources(ITCM_SECTION boards/mr_navq95a_itcm_linker.ld) zephyr_code_relocate(LIBRARY nanopb LOCATION ITCM_TEXT) diff --git a/app/rdd2/boards/mr_navq95b_m7_flash.conf b/app/rdd2/boards/mr_navq95b_m7_flash.conf new file mode 100644 index 00000000..f9adfdc8 --- /dev/null +++ b/app/rdd2/boards/mr_navq95b_m7_flash.conf @@ -0,0 +1,162 @@ +CONFIG_ENTROPY_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_SPEED_OPTIMIZATIONS=n +CONFIG_SIZE_OPTIMIZATIONS=n +CONFIG_DEBUG_OPTIMIZATIONS=y +CONFIG_CODE_DATA_RELOCATION=y + +CONFIG_TEST=y +CONFIG_UBSAN=n +CONFIG_ASSERT=y +CONFIG_ASSERT_LEVEL=2 +CONFIG_ASSERT_VERBOSE=y +CONFIG_CODE_DATA_RELOCATION=y + +CONFIG_CMSIS_DSP=y +CONFIG_CMSIS_DSP_FILTERING=y + + +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 + +CONFIG_STACK_CANARIES=y + +CONFIG_ISR_STACK_SIZE=2048 +CONFIG_SHELL_STACK_SIZE=4096 + +CONFIG_LOG_MODE_DEFERRED=y +CONFIG_LOG_MODE_IMMEDIATE=n + +CONFIG_FPU=y + +# gains +CONFIG_CEREBRI_RDD2_THRUST_TRIM=10976 +CONFIG_CEREBRI_RDD2_THRUST_DELTA=10976 + +CONFIG_CEREBRI_RDD2_ROLL_KP=5000000 +CONFIG_CEREBRI_RDD2_PITCH_KP=5000000 +CONFIG_CEREBRI_RDD2_YAW_KP=2000000 + +CONFIG_CEREBRI_RDD2_ROLLRATE_KP=300000 +CONFIG_CEREBRI_RDD2_PITCHRATE_KP=300000 +CONFIG_CEREBRI_RDD2_YAWRATE_KP=50000 + +CONFIG_CEREBRI_RDD2_ROLLRATE_KI=50000 +CONFIG_CEREBRI_RDD2_PITCHRATE_KI=50000 +CONFIG_CEREBRI_RDD2_YAWRATE_KI=50000 + +CONFIG_CEREBRI_RDD2_ROLLRATE_IMAX=20000 +CONFIG_CEREBRI_RDD2_PITCHRATE_IMAX=20000 +CONFIG_CEREBRI_RDD2_YAWRATE_IMAX=20000 + +CONFIG_CEREBRI_RDD2_ROLLRATE_KD=10000 +CONFIG_CEREBRI_RDD2_PITCHRATE_KD=10000 +CONFIG_CEREBRI_RDD2_YAWRATE_KD=0 +CONFIG_CEREBRI_RDD2_ATTITUDE_RATE_FCUT=10000 + +CONFIG_CEREBRI_RDD2_ATTITUDE_EST_ACCEL_GAIN=140 +CONFIG_CEREBRI_RDD2_ATTITUDE_EST_MAG_GAIN=800 + +# RDD2 APPS +CONFIG_CEREBRI_RDD2_ALLOCATION=y +CONFIG_CEREBRI_RDD2_ANGULAR_VELOCITY=y +CONFIG_CEREBRI_RDD2_ATTITUDE=y +CONFIG_CEREBRI_RDD2_COMMAND=y +CONFIG_CEREBRI_RDD2_ESTIMATE=y +CONFIG_CEREBRI_RDD2_ESTIMATE_ODOMETRY_ETHERNET=n +CONFIG_CEREBRI_RDD2_FSM=y +CONFIG_CEREBRI_RDD2_LIGHTING=n +CONFIG_CEREBRI_RDD2_POSITION=y + +# disabled for first live flight +CONFIG_CEREBRI_ACTUATE_PWM_SHELL=n +CONFIG_CEREBRI_ACTUATE_SOUND=n + +# config +CONFIG_INPUT=y +CONFIG_INPUT_SBUS=y +CONFIG_INPUT_SBUS_THREAD_STACK_SIZE=1024 +CONFIG_INPUT_EVENT_DUMP=n +CONFIG_INPUT_SHELL=n +CONFIG_INPUT_MODE_SYNCHRONOUS=n +CONFIG_INPUT_SBUS_REPORT_FILTER=0 +CONFIG_INPUT_THREAD_STACK_SIZE=2048 + +CONFIG_DISK_ACCESS=n +CONFIG_FS_FATFS_EXFAT=n +CONFIG_DISK_DRIVER_SDMMC=n +CONFIG_FS_FATFS_MOUNT_MKFS=n +CONFIG_CEREBRI_SYNAPSE_LOG_SDCARD=y +CONFIG_RING_BUFFER_LARGE=y +CONFIG_ZROS_SENSE_STREAM=y +CONFIG_ZROS_SENSE_STREAM_IMU=y + +CONFIG_ICM45686_STREAM=y + +CONFIG_CEREBRI_SENSE_RC=y +CONFIG_CEREBRI_SENSE_SAFETY=n + +CONFIG_ZROS_SENSE_MAG=y +CONFIG_I3C=y +CONFIG_BMM350=y +CONFIG_BMP581=y + +CONFIG_CEREBRI_SYNAPSE_ETH_RX=y +CONFIG_CEREBRI_SYNAPSE_ETH_TX=y +CONFIG_CEREBRI_ACTUATE_LED_ARRAY=n +CONFIG_CEREBRI_SENSE_POWER=n # Needs pull-up + +CONFIG_PWM=y + +CONFIG_LED_STRIP=n +CONFIG_APA102_STRIP=n +CONFIG_ZROS_SENSE_MAG_COUNT=1 + +CONFIG_CAN=y +CONFIG_CAN_MAX_FILTER=5 +CONFIG_CAN_SHELL=y + +CONFIG_NET_DRIVERS=y + +CONFIG_NET_SOCKETS_CAN=y +CONFIG_NET_DEFAULT_IF_CANBUS_RAW=y + +CONFIG_CAN_LOG_LEVEL_DBG=n +CONFIG_CAN_FD_MODE=y +CONFIG_SHELL_ARGC_MAX=72 +CONFIG_I2C=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=y +CONFIG_HEAP_MEM_POOL_SIZE=16384 + +# Debugging +CONFIG_DEBUG_THREAD_INFO=y + +# Logging +#CONFIG_LOG_BACKEND_NET=n +#CONFIG_LOG_BACKEND_NET_SERVER="192.0.2.2" + +# RPMsg +CONFIG_IPM=y +CONFIG_IPM_MBOX=y +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_OPENAMP=y +CONFIG_OPENAMP_COPY_RSC_TABLE=y +CONFIG_OPENAMP_RSC_TABLE_NUM_RPMSG_BUFF=8 +CONFIG_OPENAMP_RSC_TABLE=y +CONFIG_OPENAMP_MASTER=n +CONFIG_OPENAMP_WITH_DCACHE=y +CONFIG_CEREBRI_SYNAPSE_RPMSG=y + +# TTY over RPMsg (uncomment block below to enable) +#CONFIG_SHELL_BACKEND_RPMSG=y +#CONFIG_SHELL_BACKEND_SERIAL=n +#CONFIG_ASSERT=n + +# Disable fat and enable rpmsgfs +CONFIG_FILE_SYSTEM_RPMSGFS=y +CONFIG_FAT_FILESYSTEM_ELM=n +CONFIG_FILE_SYSTEM_SHELL=y + +# Disable atomic 64 support otherwise open-amp cannot be linked +CONFIG_COMPILER_OPT="-DNO_ATOMIC_64_SUPPORT" diff --git a/app/rdd2/boards/mr_navq95b_m7_flash.overlay b/app/rdd2/boards/mr_navq95b_m7_flash.overlay new file mode 100644 index 00000000..4429a18f --- /dev/null +++ b/app/rdd2/boards/mr_navq95b_m7_flash.overlay @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2025 CogniPilot Foundation */ +#include +#include +#include +#include +#include +#include +#include + +/ { + dshot_actuators: dshot_actuators { + compatible = "cerebri,dshot-actuators"; + aux0 { + input-type = "velocity"; + input-index = <3>; + center = <200>; + scale = <1500>; + scale-div = <1000>; + }; + aux1 { + input-type = "velocity"; + input-index = <2>; + center = <200>; + scale = <1500>; + scale-div = <1000>; + }; + aux2 { + input-type = "velocity"; + input-index = <1>; + center = <200>; + scale = <1500>; + scale-div = <1000>; + }; + aux3 { + input-type = "velocity"; + input-index = <0>; + center = <200>; + scale = <1500>; + scale-div = <1000>; + }; + }; + + chosen { + /* zephyr,canbus = &flexcan5; */ + + zephyr,ipc_shm = &shmem; + zephyr,ipc_rsc_table = &rsc_table; + zephyr,ipc = &mailbox0; + }; + + ocram: memory@20480000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x20480000 DT_SIZE_K(256)>; + zephyr,memory-region = "OCRAM"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + ddr: ddr@90000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x90000000 DT_SIZE_M(4)>; + zephyr,memory-region = "DDR"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + shmem: memory@88000000 { + compatible = "mmio-sram"; + reg = <0x88000000 0x500000>; + }; + + rsc_table: memory@88220000 { + compatible = "mmio-sram"; + reg = <0x88220000 0x100>; + }; + + mailbox0: mailbox { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mu7 1>, <&mu7 1>; + mbox-names = "tx", "rx"; + status = "okay"; + }; + + aliases { + imu-stream-0 = &icm45686; + mag0 = &bmm350; + power0 = &ina230; + rc = &sbus0; + /* can0 = &flexcan5; */ + }; +}; + +/* Some attempt at rotation */ + +&icm45686 { + axis-align-x = ; + axis-align-y = ; + axis-align-z = ; + axis-align-y-sign = ; + axis-align-z-sign = ; +}; + +&bmm350 { + axis-align-x = ; + axis-align-y = ; + axis-align-z = ; + axis-align-x-sign = ; + axis-align-z-sign = ; +}; + +/* BMI088 not supported yet with streaming +&bmi08x_accel { + axis-align-x = ; + axis-align-y = ; + axis-align-z = ; + axis-align-x-sign = ; +}; + +&bmi08x_gyro { + axis-align-x = ; + axis-align-y = ; + axis-align-z = ; + axis-align-x-sign = ; +};*/ + +&tpm5 { + prescaler = <4>; +}; + +&lpi2c6 { + clock-frequency = ; + + ina230: ina230@41 { + compatible = "ti,ina230"; + reg = <0x41>; + current-lsb-microamps = <10000>; + rshunt-micro-ohms = <2000>; + }; +}; + +&lpuart5 { + status = "okay"; + current-speed = <100000>; + rx-invert; + + sbus0: sbus { + compatible = "futaba,sbus"; + chan_1 { + channel = <1>; + type = ; + zephyr,code = <1>; + }; + chan_2 { + channel = <2>; + type = ; + zephyr,code = <2>; + }; + chan_3 { + channel = <3>; + type = ; + zephyr,code = <3>; + }; + chan_4 { + channel = <4>; + type = ; + zephyr,code = <4>; + }; + chan_5 { + channel = <5>; + type = ; + zephyr,code = <5>; + }; + chan_6 { + channel = <6>; + type = ; + zephyr,code = <6>; + }; + chan_7 { + channel = <7>; + type = ; + zephyr,code = <7>; + }; + chan_8 { + channel = <8>; + type = ; + zephyr,code = <8>; + }; + chan_9 { + channel = <9>; + type = ; + zephyr,code = <9>; + }; + chan_10 { + channel = <10>; + type = ; + zephyr,code = <10>; + }; + chan_11 { + channel = <11>; + type = ; + zephyr,code = <11>; + }; + chan_12 { + channel = <12>; + type = ; + zephyr,code = <12>; + }; + chan_13 { + channel = <13>; + type = ; + zephyr,code = <13>; + }; + chan_14 { + channel = <14>; + type = ; + zephyr,code = <14>; + }; + chan_15 { + channel = <15>; + type = ; + zephyr,code = <15>; + }; + chan_16 { + channel = <16>; + type = ; + zephyr,code = <16>; + }; + }; +}; + +&mu7 { + status = "okay"; +}; + +/* DSHOT */ + +&pinctrl { + + pinmux_dshot_j12: pinmux_dshot_j12 { + group0 { + pinmux = <&iomuxc_gpio_io04_flexio_flexio_bit_flexio1_flexio_bit4>, + <&iomuxc_gpio_io20_flexio_flexio_bit_flexio1_flexio_bit20>, + <&iomuxc_gpio_io24_flexio_flexio_bit_flexio1_flexio_bit24>, + <&iomuxc_gpio_io05_flexio_flexio_bit_flexio1_flexio_bit5>, + <&iomuxc_gpio_io21_flexio_flexio_bit_flexio1_flexio_bit21>, + <&iomuxc_gpio_io06_flexio_flexio_bit_flexio1_flexio_bit6>; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + bias-pull-up; + input-enable; + }; + }; + + lpuart7_sbus: lpuart7_sbus { + group0 { + pinmux = <&iomuxc_gpio_io08_lpuart_tx_lpuart7_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; +}; + +&flexio1 { + status = "okay"; + + dshot: dshot { + compatible = "nxp,flexio-dshot"; + pinctrl-0 = <&pinmux_dshot_j12>; + pinctrl-names = "default"; + status = "okay"; + speed = <300>; + + ch1 { + pin-id = <4>; + }; + + ch2 { + pin-id = <20>; + }; + + ch3 { + pin-id = <24>; + }; + + ch4 { + pin-id = <5>; + }; + + }; + +}; + From 47aea275534399207b4a3ec36ca10753a10c8047 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Thu, 15 Jan 2026 15:54:53 +0100 Subject: [PATCH 4/4] update_launch: Add PyOCD support Signed-off-by: Peter van der Perk --- scripts/update_launch.py | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/scripts/update_launch.py b/scripts/update_launch.py index 9800e1ee..d1986c91 100644 --- a/scripts/update_launch.py +++ b/scripts/update_launch.py @@ -112,6 +112,41 @@ "device": device, "gdbPath": gdb_path, } +elif debug_runner == "pyocd": + # Extract GDB path + gdb_path = runner_data.get("config", {}).get("gdb") + if not gdb_path: + raise ValueError("GDB path not found in runner.yaml") + + # Extract device from runner args + device = None + + serverArgs = list() + + for arg in runner_args: + if "--device=" in arg: + device = arg.split("=", 1)[1] + elif "--target=" in arg: + device = arg.split("=", 1)[1] + elif 'vtor=' in arg: + serverArgs.append("-O") + serverArgs.append("vtor=" + arg.split('=')[1]) + elif '--frequency=' in arg: + serverArgs.append("--frequency=" + arg.split('=')[1]) + + if device is None: + raise ValueError(f"Could not find device in runner args for {debug_runner}") + + update_fields = { + "name": config_name, + "type": "cortex-debug", + "request": "launch", + "executable": elf_file, + "servertype": debug_runner, + "targetId": device, + "gdbPath": gdb_path, + "serverArgs": serverArgs + } # Look for existing config for i, cfg in enumerate(launch_data["configurations"]):