diff --git a/.github/workflows/build_micropython_xiao_ra4m1.yml b/.github/workflows/build_micropython_xiao_ra4m1.yml
index 3d0e555..554f431 100644
--- a/.github/workflows/build_micropython_xiao_ra4m1.yml
+++ b/.github/workflows/build_micropython_xiao_ra4m1.yml
@@ -46,12 +46,22 @@ jobs:
       # Build MicroPython for Xiao RA4M1
       - name: Build for Xiao RA4M1
         run: |
-          cd lib && rm -r micropython || true
-          git clone https://github.com/micropython/micropython.git
-          cd micropython && git submodule update --init --recursive && gh pr checkout 16409
-          cd ports/renesas-ra 
-          sed -i '301,302c\    mp_cstack_init_with_top(&_estack, (char *)&_estack - (char *)&_sstack);' main.c
-          sed -i '170s/#define MICROPY_FATFS_ENABLE_LFN.*/#define MICROPY_FATFS_ENABLE_LFN       (1)/' mpconfigport.h
+          # Build at the repo-wide MicroPython pin (v1.27.0, the lib/micropython
+          # submodule checked out by actions/checkout) and apply the repo patch
+          # set.  The old flow cloned micropython fresh and checked out upstream
+          # PR #16409 (open, unmerged since 2024-12).  What this board actually
+          # needs from that PR is only the USB LDO VDCEN enable -- the XIAO
+          # RA4M1 powers USB from the internal LDO (USB_CFG_LDO_REGULATOR =
+          # ENABLE in the board's FSP config), now carried as
+          # 0002-renesas-ra-usb-ldo-vdcen.patch.  The WEACT board profile half
+          # of #16409 is not needed: this repo supplies the board via
+          # boards/seeed/xiao_ra4m1 and the port's native BOARD_DIR support.
+          # v1.27.0 already ships the RA4M1 family (EK_RA4M1, RA4M1_CLICKER,
+          # ra4m1_af.csv), and both old sed hacks are obsolete: main.c now
+          # contains mp_cstack_init_with_top() as-is, and
+          # MICROPY_FATFS_ENABLE_LFN is (2) (enabled, dynamic buffer).
+          ./tools/apply_micropython_patches.sh
+          cd lib/micropython/ports/renesas-ra
           make BOARD_DIR=../../../../boards/seeed/xiao_ra4m1
         env:
           GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}
diff --git a/boards/seeed/xiao_ra4m1/mpconfigboard.mk b/boards/seeed/xiao_ra4m1/mpconfigboard.mk
index c888cba..bb70fe2 100644
--- a/boards/seeed/xiao_ra4m1/mpconfigboard.mk
+++ b/boards/seeed/xiao_ra4m1/mpconfigboard.mk
@@ -1,6 +1,6 @@
 CMSIS_MCU = RA4M1
 MCU_SERIES = m4
-LD_FILES = boards/WEACT_RA4M1_CORE/ra4m1_ek.ld
+LD_FILES = $(BOARD_DIR)/ra4m1_ek.ld
 
 # MicroPython settings
 MICROPY_VFS_LFS2 = 0
@@ -15,4 +15,5 @@ CFLAGS+=-DDEFAULT_DBG_CH=0 \
           -DBOARD_TUD_RHPORT=0
 
 # Don't include default frozen modules because MCU is tight on flash space
-FROZEN_MANIFEST ?= boards/WEACT_RA4M1_CORE/manifest.py
+# (the board's own minimal manifest: asyncio only)
+FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
diff --git a/micropython/patches/v1.27.0/0002-renesas-ra-usb-ldo-vdcen.patch b/micropython/patches/v1.27.0/0002-renesas-ra-usb-ldo-vdcen.patch
new file mode 100644
index 0000000..916ceba
--- /dev/null
+++ b/micropython/patches/v1.27.0/0002-renesas-ra-usb-ldo-vdcen.patch
@@ -0,0 +1,32 @@
+diff --git a/ports/renesas-ra/main.c b/ports/renesas-ra/main.c
+--- a/ports/renesas-ra/main.c
++++ b/ports/renesas-ra/main.c
+@@ -366,6 +366,9 @@ int main(void) {
+ 
+     #if MICROPY_HW_ENABLE_USBDEV
+     mp_usbd_init();
++    #if USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE
++    mp_hal_usb_set_vdcen();
++    #endif
+     #endif
+ 
+     if (boot_res == BOARDCTRL_GOTO_SOFT_RESET_EXIT) {
+diff --git a/ports/renesas-ra/mphalport.h b/ports/renesas-ra/mphalport.h
+--- a/ports/renesas-ra/mphalport.h
++++ b/ports/renesas-ra/mphalport.h
+@@ -64,6 +64,15 @@ static inline void mp_hal_wake_main_task_from_isr(void) {
+     // Defined for tinyusb support, nothing needs to be done here.
+ }
+ 
++#if USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE
++#include "r_ioport.h"
++
++static inline void mp_hal_usb_set_vdcen(void) {
++    // Set VDCEN bit to enable USB LDO regulator
++    R_USB_FS0->USBMC = (R_USB_FS0_USBMC_VDCEN_Msk);
++}
++#endif
++
+ // timing functions
+ 
+ #include "irq.h"
diff --git a/micropython/patches/v1.27.0/README.md b/micropython/patches/v1.27.0/README.md
index c7ce557..0da8477 100644
--- a/micropython/patches/v1.27.0/README.md
+++ b/micropython/patches/v1.27.0/README.md
@@ -13,3 +13,21 @@ It adds the Zephyr-port integration required by the XIAO nRF54LM20B board:
 
 The external-flash LittleFS mount/format path is supplied by the upstream
 v1.27 `_boot.py` frozen module, so no forked MicroPython source is required.
+
+## USB LDO VDCEN patch
+
+`0002-renesas-ra-usb-ldo-vdcen.patch` is the only part of upstream PR
+micropython/micropython#16409 (WEACT_RA4M1_CORE board profile, open since
+2024-12) that the XIAO RA4M1 build actually depends on: when the board's FSP
+config enables the internal USB LDO regulator (`USB_CFG_LDO_REGULATOR`), the
+VDCEN bit in `USBMC` must be set before USB enumerates.  The WEACT board
+profile itself is not carried — this repo supplies the XIAO board definition
+via `boards/seeed/xiao_ra4m1` and the port's native `BOARD_DIR` support, and
+v1.27.0 already ships the RA4M1 family (`EK_RA4M1`, `RA4M1_CLICKER`).
+
+Both patches are applied to every job that runs
+`tools/apply_micropython_patches.sh`.  They touch disjoint file sets (0001:
+`ports/zephyr/*`, 0002: `ports/renesas-ra/*`), so a patch is inert for boards
+whose port does not compile those files, and the `VDCEN` code is additionally
+guarded by `#if USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE` so it compiles to
+nothing on boards that do not use the internal LDO.