diff --git a/pslab/bus/__init__.py b/pslab/bus/__init__.py index a235472..4e5f39c 100644 --- a/pslab/bus/__init__.py +++ b/pslab/bus/__init__.py @@ -1,7 +1,5 @@ """Contains modules for interfacing with the PSLab's I2C, SPI, and UART buses.""" -import sys - class classmethod_(classmethod): """Support chaining classmethod and property.""" @@ -11,11 +9,11 @@ def __init__(self, f): super().__init__(f) def __get__(self, obj, cls=None): - # classmethod() to support chained decorators; new in python 3.9. - if sys.version_info < (3, 9) and isinstance(self.f, property): + if cls is None: + cls = type(obj) + if isinstance(self.f, property): return self.f.__get__(cls) - else: - return super().__get__(obj, cls) + return super().__get__(obj, cls) from pslab.bus.i2c import I2CMaster, I2CSlave # noqa: E402 diff --git a/tests/test_spi.py b/tests/test_spi.py index ecd73d9..f0d3d1a 100644 --- a/tests/test_spi.py +++ b/tests/test_spi.py @@ -30,7 +30,7 @@ CS = "LA3" SPIMaster._primary_prescaler = PPRE = 0 SPIMaster._secondary_prescaler = SPRE = 0 -PWM_FERQUENCY = SPIMaster._frequency * 2 / 3 +PWM_FREQUENCY = SPIMaster._frequency * 2 / 3 MICROSECONDS = 1e-6 RELTOL = 0.05 # Number of expected logic level changes. @@ -61,7 +61,7 @@ def slave(handler: SerialHandler) -> SPISlave: @pytest.fixture def la(handler: SerialHandler) -> LogicAnalyzer: pwm = PWMGenerator(handler) - pwm.generate(SDI[1], PWM_FERQUENCY, 0.5) + pwm.generate(SDI[1], PWM_FREQUENCY, 0.5) return LogicAnalyzer(handler) @@ -73,7 +73,7 @@ def verify_value( smp: int = 0, ): sck_ts = sck_timestamps[smp::2] - pwm_half_period = ((1 / PWM_FERQUENCY) * 1e6) / 2 # microsecond + pwm_half_period = ((1 / PWM_FREQUENCY) * 1e6) / 2 # microsecond pattern = "" for t in sck_ts: @@ -310,3 +310,27 @@ def test_transfer16_bulk(la: LogicAnalyzer, slave: SPISlave): assert len(sdo) == 0 assert verify_value(value[0], sck, sdi_initstate, sdi[:32]) assert verify_value(value[1], sck, sdi_initstate, sdi[32:]) + + +def test_frequency_property(): + """Verify that SPIMaster._frequency returns a numeric float.""" + assert isinstance(SPIMaster._frequency, float) + assert SPIMaster._frequency > 0 + master = SPIMaster.__new__(SPIMaster) + assert isinstance(master._frequency, float) + assert master._frequency == SPIMaster._frequency + + +def test_pwm_frequency_calculation(): + """Verify that PWM_FREQUENCY is correctly calculated from SPIMaster._frequency.""" + assert isinstance(PWM_FREQUENCY, float) + assert PWM_FREQUENCY == SPIMaster._frequency * 2 / 3 + + +def test_clock_phase_property(): + """Verify that SPIMaster._clock_phase returns an integer.""" + assert isinstance(SPIMaster._clock_phase, int) + assert SPIMaster._clock_phase in (0, 1) + master = SPIMaster.__new__(SPIMaster) + assert isinstance(master._clock_phase, int) + assert master._clock_phase == SPIMaster._clock_phase diff --git a/tests/test_uart.py b/tests/test_uart.py index fd861e5..f4eb0ec 100644 --- a/tests/test_uart.py +++ b/tests/test_uart.py @@ -16,7 +16,7 @@ WRITE_DATA = 0x55 TXD2 = "LA1" RXD2 = "SQ1" -PWM_FERQUENCY = UART._baudrate // 2 +PWM_FREQUENCY = UART._baudrate // 2 MICROSECONDS = 1e-6 RELTOL = 0.05 # Number of expected logic level changes. @@ -38,7 +38,7 @@ def la(handler: SerialHandler) -> LogicAnalyzer: @pytest.fixture def pwm(handler: SerialHandler) -> None: pwm = PWMGenerator(handler) - pwm.generate(RXD2, PWM_FERQUENCY, 0.5) + pwm.generate(RXD2, PWM_FREQUENCY, 0.5) def test_configure(la: LogicAnalyzer, uart: UART): @@ -82,3 +82,18 @@ def test_read_int(pwm: PWMGenerator, uart: UART): value = uart.read_int() assert value in (0x5555, 0x55AA, 0xAA55, 0xAAAA) + + +def test_baudrate_property(): + """Verify that UART._baudrate returns a numeric float.""" + assert isinstance(UART._baudrate, float) + assert UART._baudrate > 0 + uart = UART.__new__(UART) + assert isinstance(uart._baudrate, float) + assert uart._baudrate == UART._baudrate + + +def test_pwm_frequency_calculation(): + """Verify that PWM_FREQUENCY is correctly calculated from UART._baudrate.""" + assert isinstance(PWM_FREQUENCY, float) + assert PWM_FREQUENCY == UART._baudrate // 2