Arty-A7: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

[PietDelaney]

I just pulled the latest bits and give it a guick try. I got this error on downloading the bits to the Arty A7:

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

I also had a problem on the top level build and report that error seperat;y.

[davidharrishmc]

What happens if you back off the frequency?

…

On Mon, Jun 23, 2025 at 8:19 PM Pete Delaney ***@***.***> wrote: I just pulled the latest bits and give it a guick try. I got this error on downloading the bits to the Arty A7: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. I also had a problem on the top level build and report that error seperat;y. — Reply to this email directly, view it on GitHub <#1463>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA3ZJB6WXYA5DH3HDFED3FC7OJAVCNFSM6AAAAAB77AFWT6VHI2DSMVQWIX3LMV43ERDJONRXK43TNFXW4OZYGQ4DMNRTGY> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[PietDelaney]

I didn't know how to' back off the frequency' so I discussed it with chatgpt and messed around for about an hour+ and the change I finally tried doesn't see to have fixed it.

diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc
index 924cd1aea..915667dd8 100644
--- a/fpga/constraints/constraints-ArtyA7.xdc
+++ b/fpga/constraints/constraints-ArtyA7.xdc
@@ -294,3 +294,7 @@ set_property PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]
+#
+# piet: suggestion from chatgpt:
+#
+create_clock -name CPUCLK -period 50.000 [get_nets CPUCLK]

I tried doing a complete make cleanAll and make and tried again,
The Design Timinmg Summary still showed
Total Negitive State (TNS): -1.051 ns

but this time the kernel loaded and ran fine.

My guess is the error isn't serious and my change to constraints-ArtyA7.xdc likely wasn't needed
and I just didn't start the image right.

I'll revert the change and rebuild and confirm.

piet/pete

[PietDelaney]

Though:
Still getting Timing warinig:
[Timing 38-282] The design failed to meet the timing requirements.
Please see the timing summary report for details on the timing violations.

total Negitive Slack (TNS) :       -2.563 ns

Number of failed endpoints: 10

as I suspected the Wally Image did boot on the ARTY=A7.

So I guess this is a false alarm. I got confused by the serious error messages from Vivado.

Sorry/Sigh.

-piet