From bf8ca35d5a3b3c238cc5e3993072b6ce9f37a6b2 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Mon, 11 May 2026 16:12:08 +0530 Subject: [PATCH] WORKAROUND: Restore misco0 register on CPU idle exit CPU system registers are reset on entry to the idle state, which clears the required bits in the misc0 cnd ctrl register and prevents CE/UE interrupts from firing. Register a PM notifier to restore the misc0 and ctrl registers on idle exit, ensuring that interrupts are correctly triggered. This is a temporary workaround and will be reverted once the proper fix is upstreamed in v2 of this series. Signed-off-by: Umang Chheda --- ...-AEST-support-to-Device-Tree-frontend.mbox | 4468 +++++++++++++++++ drivers/ras/aest/aest-core.c | 116 +- 2 files changed, 4583 insertions(+), 1 deletion(-) create mode 100644 PATCH-0-8-ras-aest-extend-AEST-support-to-Device-Tree-frontend.mbox diff --git a/PATCH-0-8-ras-aest-extend-AEST-support-to-Device-Tree-frontend.mbox b/PATCH-0-8-ras-aest-extend-AEST-support-to-Device-Tree-frontend.mbox new file mode 100644 index 0000000000000..98738cc4865c8 --- /dev/null +++ b/PATCH-0-8-ras-aest-extend-AEST-support-to-Device-Tree-frontend.mbox @@ -0,0 +1,4468 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id C397D39BFE9 + for ; Tue, 5 May 2026 12:24:53 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 +ARC-Seal:i=1; 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This series adds a DT frontend that mirrors the ACPI +implementation and feeds the same core driver, keeping ACPI and DT +paths functionally equivalent. + +Along the way, several correctness issues were identified in the core +driver and are fixed in the first part of this series. + +The DT frontend is mutually exclusive with ACPI and does not introduce +any DT-specific logic into the core. + +How to test with QEMU +-------------------------- +Tian Ruidong's QEMU fork [2] emulates AEST MMIO error records on the +virt machine. To test the DT frontend: + +1. Build QEMU: + + git clone https://github.com/winterddd/qemu.git + cd qemu + git checkout c5e2d5dec9fd62ba622314c40bff0fbecb4dfb34 + ./configure --target-list=aarch64-softmmu + make -j$(nproc) + +2. Build the kernel with: + + CONFIG_OF_AEST=y + CONFIG_AEST=y + CONFIG_ARM64_RAS_EXTN=y + CONFIG_RAS=y + +3. Add the following DT node to your virt machine DTB. The QEMU + fork maps DRAM error records at 0x090d0000 (SPI 44) and CMN + vendor records at 0x090e0000 (SPI 45): + + aest { + compatible = "arm,aest"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-parent = <&gic>; + + /* DRAM memory node — MMIO at 0x090d0000, SPI 44 */ + aest-dram0@90d0000 { + compatible = "arm,aest-memory"; + arm,interface-type = <1>; + arm,group-format = <0>; + arm,interface-flags = <0x22>; + arm,num-records = <4>; + arm,record-impl = /bits/ 64 <0x0>; + arm,status-report = /bits/ 64 <0x0>; + arm,addr-mode = /bits/ 64 <0x0>; + arm,proximity-domain = <0>; + reg = <0x0 0x090d0000 0x0 0x1000>, + <0x0 0x090d0800 0x0 0x200>, + <0x0 0x090d0e00 0x0 0x100>; + reg-names = "errblock", "fault-inject", + "err-group"; + interrupts = ; + interrupt-names = "fhi"; + }; + }; + +4. Boot QEMU with acpi=off: + + ./qemu-system-aarch64 \ + -machine virt,accel=tcg,gic-version=3 \ + -cpu cortex-a57 -m 2G -smp 4 \ + -kernel Image -dtb virt-aest.dtb \ + -append "console=ttyAMA0 acpi=off earlycon" \ + -nographic + +5. Verify probe: + + dmesg | grep "DT AEST" + # Expected: DT AEST: registered 1 AEST error source(s) from DT + ls /sys/kernel/debug/aest/ + +6. Inject a CE error via the QEMU MMIO fault injection registers. + The QEMU device accepts 64-bit accesses only (use devmem with + the 64-bit width flag): + + devmem 0x090d0808 64 0x80000040 # CDOFF | CE inject + + This triggers QEMU's error_record_inj_write() which sets + ERRSTATUS.V=1 and asserts the IRQ. The kernel driver's + aest_irq_func() fires, reads the status, and logs: + + AEST: {1}[Hardware Error]: Hardware error from AEST memory.90d0000 + AEST: {1}[Hardware Error]: Error from memory at SRAT proximity domain 0x0 + +Testing +------- +- Validated on Qualcomm's lemans-evk and monaco-evk board with DT boot. +- Validated CE and UE injection via debugfs soft_inject. +- Tested ACPI path is unaffected: ACPI boot continues to use + drivers/acpi/arm64/aest.c unchanged. + +[1] https://lore.kernel.org/lkml/20260122094656.73399-1-tianruidong@linux.alibaba.com/ +[2] https://github.com/winterddd/qemu/tree/error_record +[3] https://developer.arm.com/documentation/den0085/0200/ + +Signed-off-by: Umang Chheda +--- +Umang Chheda (8): + ras: aest: Fix shared processor node handling and error log messages + ras: aest: Fix CE/UE error counts not incrementing in debugfs + ras: aest: Skip unimplemented records in debugfs + ras: aest: Add panic_on_ue module parameter + dt-bindings: arm: ras: Introduce bindings for ARM AEST + ras: aest: Add DT frontend for ARM AEST RAS error sources + arm64: dts: qcom: lemans: add AEST error nodes + arm64: dts: qcom: monaco: add AEST error nodes + + .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++ + arch/arm64/boot/dts/qcom/lemans.dtsi | 41 ++ + arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++ + drivers/ras/aest/Kconfig | 15 +- + drivers/ras/aest/Makefile | 2 + + drivers/ras/aest/aest-core.c | 63 +- + drivers/ras/aest/aest-of.c | 673 +++++++++++++++++++++ + drivers/ras/aest/aest-sysfs.c | 27 +- + drivers/ras/aest/aest.h | 15 +- + include/dt-bindings/arm/aest.h | 43 ++ + 10 files changed, 1310 insertions(+), 16 deletions(-) +--- +base-commit: a67b7fd0dd1f6ccf3d128dc2099cdb07af1f6a09 +change-id: 20260505-aest-devicetree-support-a3722d90e1f5 +prerequisite-message-id: <20260122094656.73399-1-tianruidong@linux.alibaba.com> +prerequisite-patch-id: c5a7c6431c6c1e6351241e694ee053800039d41d +prerequisite-patch-id: 1f6e2c20829eee41a210dd8a538f1e8efcc65872 +prerequisite-patch-id: 5556287e3f46c2ed2c0431c53c7782e87bcbd866 +prerequisite-patch-id: 2edae0a136d7779b8f686181720e71d044a73311 +prerequisite-patch-id: b5190b2844dcb01e72f87a59f3a29548795fdb82 +prerequisite-patch-id: 7ba848583708b2ae776a7ce847bb056e3de7f77b +prerequisite-patch-id: 397e5b22802b67942435f4f2968f0b1e210ba0e8 +prerequisite-patch-id: 2169f4b65537eecbd0ccbd2ad6b28c64ec44655d +prerequisite-patch-id: b626f85d98747595b3240bc49e6ad9c9dd5c0fa9 +prerequisite-patch-id: 1323dfd2eebad2ef6514dbbce58ba08e8859f894 +prerequisite-patch-id: 95b826e5e329408437a3ef336c4f45d4d74f82bb +prerequisite-patch-id: b60ff489a5a33c5d5220fa8144af7b7511769cba +prerequisite-patch-id: 43f35a52b8a3d13c938ff08083403c1d3bd0df8b +prerequisite-patch-id: c55d4e9117ca36d3c2cba82d550a618cb82bb745 +prerequisite-patch-id: 3885e10f318ae8101d6909b35d92a976cc359e3c +prerequisite-patch-id: 92958cde05577f069c5659018a274bb39cfb6b24 + +Best regards, +-- +Umang Chheda + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 782BB4279F4 + for ; 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Only nodes whose FHI or ERI is a per-CPU PPI take the oncore + path, nodes with an SPI take aest_online_dev(). + +2. alloc_aest_node_name() uses processor_id for the node name of all + processor nodes. Shared/global nodes have processor_id=0 (the + field is unused when SHARED/GLOBAL is set), so every shared node + and the per-PE node for CPU 0 both got the name "processor.0", + making error logs ambiguous. + + For shared/global nodes, build the name as + "processor.." (e.g. "processor.cache.1") + so each node has a unique, meaningful identifier. Per-PE nodes + keep the original "processor." form. + + Also add proc_flags to struct aest_event so aest_print() can + distinguish shared from per-PE nodes and print an appropriate + message. + +Signed-off-by: Umang Chheda +--- + drivers/ras/aest/aest-core.c | 54 ++++++++++++++++++++++++++++++++++++++++---- + drivers/ras/aest/aest.h | 15 +++++++++++- + 2 files changed, 64 insertions(+), 5 deletions(-) + +diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c +index 6a2d84b47721..b4f4c975da1d 100644 +--- a/drivers/ras/aest/aest-core.c ++++ b/drivers/ras/aest/aest-core.c +@@ -49,7 +49,19 @@ static void aest_print(struct aest_event *event) + + switch (event->type) { + case ACPI_AEST_PROCESSOR_ERROR_NODE: +- pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); ++ /* ++ * For shared/global nodes (e.g. cluster L3 cache, DSU), ++ * id0 is the CPU that handled the interrupt — not the error ++ * source itself. The node_name already identifies the resource ++ * (e.g. "processor.cache.1"). Print a distinct message so the ++ * log is not confused with a per-PE CPU error. ++ */ ++ if (event->proc_flags & ++ (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) ++ pr_err("%s Error from shared processor resource (interrupt handled on CPU%d)\n", ++ pfx_seq, event->id0); ++ else ++ pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); + break; + case ACPI_AEST_MEMORY_ERROR_NODE: + pr_err("%s Error from memory at SRAT proximity domain %#x\n", +@@ -133,6 +145,7 @@ static void init_aest_event(struct aest_event *event, + info->processor->processor_id); + + event->id1 = info->processor->resource_type; ++ event->proc_flags = info->processor->flags; + break; + case ACPI_AEST_MEMORY_ERROR_NODE: + event->id0 = info->memory->srat_proximity_domain; +@@ -175,6 +188,7 @@ static int aest_node_gen_pool_add(struct aest_device *adev, + if (!event) + return -ENOMEM; + ++ memset(event, 0, sizeof(*event)); + init_aest_event(event, record, regs); + llist_add(&event->llnode, &adev->event_list); + +@@ -730,9 +744,41 @@ static char *alloc_aest_node_name(struct aest_node *node) + + switch (node->type) { + case ACPI_AEST_PROCESSOR_ERROR_NODE: +- name = devm_kasprintf(node->adev->dev, GFP_KERNEL, "%s.%d", +- aest_node_name[node->type], +- node->info->processor->processor_id); ++ /* ++ * Shared/global processor nodes (e.g. cluster L3 cache, DSU) ++ * have processor_id=0 and use smp_processor_id() at error-log ++ * time — using processor_id in the name would produce the same ++ * "processor.0" string for every shared node and every CPU0 ++ * per-PE node, making logs ambiguous. ++ * ++ * For shared/global nodes, build the name from the resource ++ * type and the device id so each node gets a unique, meaningful ++ * name (e.g. "processor.cache.1", "processor.tlb.2"). ++ * ++ * For per-PE nodes, keep the original "processor." form. ++ */ ++ if (node->info->processor->flags & ++ (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) { ++ static const char *const res_name[] = { ++ [ACPI_AEST_CACHE_RESOURCE] = "cache", ++ [ACPI_AEST_TLB_RESOURCE] = "tlb", ++ [ACPI_AEST_GENERIC_RESOURCE] = "generic", ++ }; ++ u8 rtype = node->info->processor->resource_type; ++ const char *rstr = (rtype < ARRAY_SIZE(res_name) && ++ res_name[rtype]) ? res_name[rtype] : "unknown"; ++ ++ name = devm_kasprintf(node->adev->dev, GFP_KERNEL, ++ "%s.%s.%d", ++ aest_node_name[node->type], ++ rstr, ++ node->adev->id); ++ } else { ++ name = devm_kasprintf(node->adev->dev, GFP_KERNEL, ++ "%s.%d", ++ aest_node_name[node->type], ++ node->info->processor->processor_id); ++ } + break; + case ACPI_AEST_MEMORY_ERROR_NODE: + case ACPI_AEST_SMMU_ERROR_NODE: +diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h +index 9d67d79eb4a2..9704af97fee8 100644 +--- a/drivers/ras/aest/aest.h ++++ b/drivers/ras/aest/aest.h +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + #define MAX_GSI_PER_NODE 2 + #define DEFAULT_CE_THRESHOLD 1 +@@ -94,6 +95,8 @@ struct aest_event { + /* Vendor node : hardware ID. */ + char *hid; + u32 index; ++ /* Processor node: ACPI_AEST_PROC_FLAG_* bitmask (SHARED/GLOBAL) */ ++ u8 proc_flags; + u64 ce_threshold; + int addressing_mode; + struct ras_ext_regs regs; +@@ -387,7 +390,17 @@ static inline void aest_sync(struct aest_node *node) + + static inline bool aest_dev_is_oncore(struct aest_device *adev) + { +- return adev->type == ACPI_AEST_PROCESSOR_ERROR_NODE; ++ /* ++ * A processor node is "on-core" (uses PPI + cpuhp) only when its ++ * interrupt is a per-CPU PPI. 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The IRQ handler updates CE counters in the per-CPU + records created by __setup_ppi, the template records are never touched + at runtime, so err_count always read as zero. + +Fix this by: + +- Using per_cpu_ptr(adev->adev_oncore, cpu) when iterating over CPUs. + Wiring debugfs files to percpu_dev->nodes[i] so counters reflect the + data updated by the IRQ handler. + +- Using adev->nodes[i].name for debugfs directory names. The per-CPU node + receives name via a shallow memcpy and is not the authoritative source. + +Signed-off-by: Umang Chheda +--- + drivers/ras/aest/aest-sysfs.c | 19 +++++++++++++------ + 1 file changed, 13 insertions(+), 6 deletions(-) + +diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c +index 66e9c1103f99..f710503e4d74 100644 +--- a/drivers/ras/aest/aest-sysfs.c ++++ b/drivers/ras/aest/aest-sysfs.c +@@ -189,16 +189,23 @@ aest_oncore_dev_init_debugfs(struct aest_device *adev) + char name[16]; + + for_each_possible_cpu(cpu) { +- percpu_dev = this_cpu_ptr(adev->adev_oncore); ++ percpu_dev = per_cpu_ptr(adev->adev_oncore, cpu); + +- snprintf(name, sizeof(name), "processor%u%u", cpu); ++ snprintf(name, sizeof(name), "processor%u", cpu); + percpu_dev->debugfs = debugfs_create_dir(name, adev->debugfs); + + for (i = 0; i < adev->node_cnt; i++) { +- node = &adev->nodes[i]; +- +- node->debugfs = debugfs_create_dir(node->name, +- percpu_dev->debugfs); ++ node = &percpu_dev->nodes[i]; ++ ++ /* ++ * Use adev->nodes[i].name (the original) rather than ++ * node->name from the per-CPU copy. The per-CPU copy ++ * receives node->name via shallow memcpy in __setup_ppi; ++ * the original is the authoritative, guaranteed-valid ++ * string. ++ */ ++ node->debugfs = debugfs_create_dir(adev->nodes[i].name, ++ percpu_dev->debugfs); + aest_node_init_debugfs(node); + } + } + +-- +2.34.1 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 104EB42B721 + for ; Tue, 5 May 2026 12:25:12 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 +ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; + t=1777983915; cv=none; b=BTTPJsR/AwML3HENpfXcFEVzaW79agO04tTh76/lD5V9EIX3K846NxWKTDfamojH1FC5dFmVei12AO/XHppjbn7DzfWzn4/YKIaUSwJbXASO0Nxe5eqtA1yXiwilFDOof953sLLxswea5EsZFmY/ZWIdM5lhh32sS4ypu8okSkw= +ARC-Message-Signature:i=1; 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There is no way +for the user to suppress this behaviour, which makes it difficult to +test UE injection or to run in environments where a kernel panic on +every UE is undesirable. + +Add a module parameter `aest_panic_on_ue` When set to 0 the driver +logs the UE and continues instead of panicking. + +Usage: + # Boot time (kernel cmdline) + aest.aest_panic_on_ue=0 + + # Runtime + echo 0 > /sys/module/aest/parameters/aest_panic_on_ue + +Signed-off-by: Umang Chheda +--- + drivers/ras/aest/aest-core.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c +index b4f4c975da1d..9ce782a66edf 100644 +--- a/drivers/ras/aest/aest-core.c ++++ b/drivers/ras/aest/aest-core.c +@@ -22,6 +22,11 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); + #undef pr_fmt + #define pr_fmt(fmt) "AEST: " fmt + ++static bool aest_panic_on_ue; ++module_param(aest_panic_on_ue, bool, 0644); ++MODULE_PARM_DESC(aest_panic_on_ue, ++ "Panic on unrecoverable error: 0=off 1=on (default: 1)"); ++ + #ifdef CONFIG_DEBUG_FS + struct dentry *aest_debugfs; + #endif +@@ -342,9 +347,11 @@ void aest_proc_record(struct aest_record *record, void *data, bool fake) + aest_record_info( + record, + "Simulated error! Skip panic due to fault injection\n"); +- else ++ else if (aest_panic_on_ue) + aest_panic(record, ®s, + "AEST: unrecoverable error encountered"); ++ else ++ aest_record_err(record, "UE detected, panic suppressed\n"); + } + + aest_log(record, ®s); + +-- +2.34.1 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id E366E436372 + for ; Tue, 5 May 2026 12:25:26 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 +ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; + t=1777983928; cv=none; b=P9rZjF27xGpq2g+8C4rgj3uRXvyB0xjKI3JsEmW5i4HsMKEr3TZ+l/pGI4QTKOHL0qTJuOWvFoViaA/NFcFj+HkqRSP+jU6KJHzU/U42I/oEG1FfQnw2ILT3T4hU+SfaD8J70xpm3A5JtL1uMxQfKT+KUBbDj2P3e9r+4vA88QM= +ARC-Message-Signature:i=1; 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a=ed25519-sha256; t=1777983885; l=17370; + i=umang.chheda@oss.qualcomm.com; s=20260328; h=from:subject:message-id; + bh=UHYiBMmAeYcwT/oKI59kIU40Oa6oQXNeQvw8DW7wwUc=; + b=f4X30PASN24PpuxlrbpxYQZBWzx209SeZljlnp69AjiGRkj+36R5vxwg3Qy5cQBrM/hbFOpjx + u4UP5xT2z8ODHJb/19T3Ngha9QvMUP2gtbjutRuGfrAcWKWTjmmt8b6 +X-Developer-Key: i=umang.chheda@oss.qualcomm.com; a=ed25519; + pk=3+tjZ+PFFYphz0Vvu4B14pBQSzqcG0jZAQspTaDRQYA= +X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA1MDExNyBTYWx0ZWRfXy95S6I0o6E1s + MVZDziJhLZ+BBJeI9bKv/2PbbKyKCgm//Uv+nsFGW5RuanxkA+t869Q+hg1qM0qKuHVVQnsoEyQ + 0Al8E0vf//aekk6ZmtvLTRCy6/FSrvBqK2G+C23F38l/11oVZeZnxq2QhSfXtMGYXrK9iSeBSH8 + aBBc6MmWnD7OXuilGfEJgGdmetmM/UXQ3RmHWAPg5NsFzVQukLzvs3jreUBvKT44rQliD+fAHPA + yJxbpHGdR0c7YO2xckTF9jKtZ9vd8yghfWlHL44I51NO4NWVFzNqkv77lfvpR1cFKqRxnEHWXXV + 1ybHzkQjB1mk8Y02RI3u9+bsBnJOpxnKZpZL8cLAFz16kDJ8C/LQjnD8DjoD/kdLtVZn9hixHOU + 6jCS/kf26ySAQ+aA4Dq2w6uMjeT2kwruvz9LtmO9ixO9TRtmR/3P+aB0aeI1GB57oHu2K2CubKv + FF3ETv6yebqEh2fZ+UQ== +X-Proofpoint-ORIG-GUID: 3_-ATaULrdlTPREMbi-6W-k8xWi43yEo +X-Proofpoint-GUID: 3_-ATaULrdlTPREMbi-6W-k8xWi43yEo +X-Authority-Analysis: v=2.4 cv=edoNubEH c=1 sm=1 tr=0 ts=69f9e1b5 cx=c_pps + a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 + a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 + a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 + a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=vTNCWx79gXjKDdEYbRgA:9 a=QEXdDO2ut3YA:10 + a=OpyuDcXvxspvyRM73sMx:22 a=sptkURWiP4Gy88Gu7hUp:22 +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 + definitions=2026-05-05_02,2026-04-30_02,2025-10-01_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 + priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 + lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= + route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 + definitions=main-2605050117 + +The Arm Error Source Table (AEST) specification describes how firmware +exposes RAS error source topology to the operating system. On ACPI +systems this information is provided via the AEST ACPI table. + +Introduce Device Tree bindings that provide an equivalent description +of AEST error sources for DT-based platforms. + +Signed-off-by: Umang Chheda +--- + .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++++++++++ + include/dt-bindings/arm/aest.h | 43 +++ + 2 files changed, 449 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/arm,aest.yaml b/Documentation/devicetree/bindings/arm/arm,aest.yaml +new file mode 100644 +index 000000000000..7809a0d38270 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/arm,aest.yaml +@@ -0,0 +1,406 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/arm/arm,aest.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Arm Error Source Table (AEST) ++ ++maintainers: ++ - Umang Chheda ++ ++description: ++ The Arm Error Source Table (AEST) describes RAS error sources and their ++ register interfaces. Each error source exposes one or more error records ++ through either system registers or a memory-mapped register window, and ++ may signal errors via interrupts. The top-level node acts as a container ++ for one or more child nodes, each describing a single AEST error source. ++ Refer to the Arm AEST specification (DEN0085 / DDI 0587B) for details. ++ Flag bit constants for use in DT source files are defined in ++ . ++ ++properties: ++ compatible: ++ const: arm,aest ++ ++ "#address-cells": ++ const: 2 ++ ++ "#size-cells": ++ const: 2 ++ ++ ranges: true ++ ++required: ++ - compatible ++ ++additionalProperties: false ++ ++patternProperties: ++ "^aest-[a-z0-9-]+(@[0-9a-f]+)?$": ++ type: object ++ description: ++ An AEST error source node describing one error source defined by ++ the Arm AEST specification. ++ ++ properties: ++ compatible: ++ description: ++ Identifies the type of AEST error source. Each value corresponds to ++ a distinct error source class defined by the Arm AEST specification. ++ arm,aest-proxy represents a proxy error source that forwards errors ++ from another error source. ++ enum: ++ - arm,aest-processor ++ - arm,aest-memory ++ - arm,aest-smmu ++ - arm,aest-gic ++ - arm,aest-pcie ++ - arm,aest-vendor ++ - arm,aest-proxy ++ ++ reg: ++ description: ++ Register ranges for the error source. Absence of reg implies ++ system-register access (interface type 0). A single range implies ++ memory-mapped access (interface type 1). Two ranges imply ++ single-record memory-mapped access (interface type 2). ++ minItems: 1 ++ maxItems: 4 ++ ++ reg-names: ++ description: ++ Names for the register ranges. The base error-record window is ++ unnamed (or first entry). Optional named ranges provide access to ++ the fault-injection, error-group, and interrupt-config register ++ windows defined by the AEST specification. ++ minItems: 1 ++ maxItems: 4 ++ items: ++ enum: ++ - fault-inject ++ - err-group ++ - irq-config ++ ++ interrupts: ++ description: Interrupts associated with the error source. ++ minItems: 1 ++ maxItems: 2 ++ ++ interrupt-names: ++ description: Names of the interrupts associated with the error source. ++ minItems: 1 ++ maxItems: 2 ++ items: ++ enum: ++ - fhi ++ - eri ++ ++ arm,fhi-flags: ++ description: ++ Bitmask of flags for the fault-handling interrupt (FHI), as defined ++ in the AEST node interrupt structure flags field. Constants are ++ defined in - AEST_IRQ_MODE_LEVEL (0), ++ AEST_IRQ_MODE_EDGE (1). ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,eri-flags: ++ description: ++ Bitmask of flags for the error-recovery interrupt (ERI), as defined ++ in the AEST node interrupt structure flags field. Constants are ++ defined in . ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,interface-flags: ++ description: | ++ Bitmask of interface flags for the error source, as defined in the ++ AEST node interface flags field. Constants are defined in ++ : ++ AEST_XFACE_SHARED (bit 0) - shared error source, ++ AEST_XFACE_CLEAR_MISC (bit 1) - clear MISC registers on error, ++ AEST_XFACE_ERROR_DEVICE (bit 2) - error node device present, ++ AEST_XFACE_AFFINITY (bit 3) - affinity information valid, ++ AEST_XFACE_ERROR_GROUP (bit 4) - error group register window present, ++ AEST_XFACE_FAULT_INJECT (bit 5) - fault injection register window present, ++ AEST_XFACE_INT_CONFIG (bit 6) - interrupt config register window present. ++ For system-register interface nodes (no reg property), only ++ AEST_XFACE_CLEAR_MISC is meaningful; the MMIO window flags ++ (AEST_XFACE_ERROR_GROUP, AEST_XFACE_FAULT_INJECT, ++ AEST_XFACE_INT_CONFIG) have no effect without a base address. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,group-format: ++ description: | ++ Page-granularity of the error record group register window, which ++ determines the MMIO mapping size, the number of ERRGSR registers, ++ and the width of the record-implemented and status-reporting bitmaps. ++ Constants are defined in : ++ AEST_GROUP_FORMAT_4K (0) - 4K window, 1 ERRGSR, up to 64 records, ++ AEST_GROUP_FORMAT_16K (1) - 16K window, 4 ERRGSRs, up to 256 records, ++ AEST_GROUP_FORMAT_64K (2) - 64K window, 14 ERRGSRs, up to 896 records. ++ Required for memory-mapped nodes (reg present) where it controls ++ the ioremap size and ERRGSR layout. For system-register nodes ++ (no reg property) this property is optional and defaults to ++ AEST_GROUP_FORMAT_4K. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [0, 1, 2] ++ ++ arm,num-records: ++ description: Number of error records implemented by this error source. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,record-impl: ++ description: ++ Bitmap of implemented error records within this error source. Bit N ++ set to 0 means error record N is implemented and must be polled. ++ $ref: /schemas/types.yaml#/definitions/uint64-array ++ ++ arm,status-reporting: ++ description: ++ Bitmap indicating which error records support status reporting via ++ the ERRGSR register. Bit N set to 1 means record N does not report ++ through ERRGSR and must be polled explicitly. ++ $ref: /schemas/types.yaml#/definitions/uint64-array ++ ++ arm,addressing-mode: ++ description: ++ Bitmap indicating the address type reported in ERR_ADDR for each ++ error record. Bit N set to 0 means record N reports System Physical ++ Addresses (SPA); bit N set to 1 means record N reports node-specific ++ Logical Addresses (LA) that require OS translation to SPA. ++ $ref: /schemas/types.yaml#/definitions/uint64-array ++ ++ arm,processor-flags: ++ description: ++ Bitmask indicating the scope of a processor error source, as defined ++ in the AEST processor node flags field. Constants are defined in ++ - AEST_PROC_GLOBAL (bit 0), ++ AEST_PROC_SHARED (bit 1). ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,resource-type: ++ description: | ++ Type of processor resource associated with this error source. ++ Constants are defined in : ++ AEST_RESOURCE_CACHE (0), ++ AEST_RESOURCE_TLB (1), ++ AEST_RESOURCE_GENERIC (2). ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [0, 1, 2] ++ ++ arm,cache-ref: ++ description: ++ Phandle to the cache node associated with this processor error source. ++ $ref: /schemas/types.yaml#/definitions/phandle ++ ++ arm,tlb-level: ++ description: TLB level identifier for this processor TLB error source. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,resource-ref: ++ description: ++ Generic resource reference identifier for this processor error source. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,proximity-domain: ++ description: ++ SRAT proximity domain of the memory node associated with this error ++ source. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,smmu-ref: ++ description: ++ Phandle to the SMMU node in the IORT associated with this error ++ source. ++ $ref: /schemas/types.yaml#/definitions/phandle ++ ++ arm,smmu-subcomponent: ++ description: ++ SMMU subcomponent reference identifier for this error source, as ++ defined in the AEST SMMU node structure. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,gic-type: ++ description: | ++ GIC component type for this error source, as defined in the AEST GIC ++ node structure. Constants are defined in : ++ AEST_GIC_CPU (0), ++ AEST_GIC_DISTRIBUTOR (1), ++ AEST_GIC_REDISTRIBUTOR (2), ++ AEST_GIC_ITS (3). ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [0, 1, 2, 3] ++ ++ arm,gic-instance: ++ description: ++ GIC instance identifier for this error source, used to distinguish ++ multiple instances of the same GIC component type. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,pcie-segment: ++ description: ++ PCI segment number of the PCIe root port associated with this error ++ source, corresponding to the IORT node reference. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ arm,vendor-hid: ++ description: ++ 8-character ACPI Hardware ID string identifying the vendor error ++ source, as defined in the AEST vendor node structure. ++ $ref: /schemas/types.yaml#/definitions/string ++ ++ arm,vendor-uid: ++ description: ++ ACPI unique instance identifier for this vendor error source, used ++ to distinguish multiple instances with the same hardware ID. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ ++ required: ++ - compatible ++ - arm,num-records ++ ++ allOf: ++ - if: ++ required: ++ - reg ++ then: ++ required: ++ - arm,group-format ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: arm,aest-processor ++ then: ++ properties: ++ arm,processor-flags: {} ++ arm,resource-type: {} ++ arm,cache-ref: {} ++ arm,tlb-level: {} ++ arm,resource-ref: {} ++ else: ++ properties: ++ arm,processor-flags: false ++ arm,resource-type: false ++ arm,cache-ref: false ++ arm,tlb-level: false ++ arm,resource-ref: false ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: arm,aest-memory ++ then: ++ required: ++ - arm,proximity-domain ++ properties: ++ arm,proximity-domain: {} ++ else: ++ properties: ++ arm,proximity-domain: false ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: arm,aest-smmu ++ then: ++ required: ++ - arm,smmu-ref ++ properties: ++ arm,smmu-ref: {} ++ arm,smmu-subcomponent: {} ++ else: ++ properties: ++ arm,smmu-ref: false ++ arm,smmu-subcomponent: false ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: arm,aest-gic ++ then: ++ properties: ++ arm,gic-type: {} ++ arm,gic-instance: {} ++ else: ++ properties: ++ arm,gic-type: false ++ arm,gic-instance: false ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: arm,aest-pcie ++ then: ++ required: ++ - arm,pcie-segment ++ properties: ++ arm,pcie-segment: {} ++ else: ++ properties: ++ arm,pcie-segment: false ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: arm,aest-vendor ++ then: ++ required: ++ - arm,vendor-hid ++ properties: ++ arm,vendor-hid: {} ++ arm,vendor-uid: {} ++ else: ++ properties: ++ arm,vendor-hid: false ++ arm,vendor-uid: false ++ ++ unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ aest { ++ compatible = "arm,aest"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ /* System-register based processor error source (no reg property) */ ++ aest-processor-0 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <2>; ++ arm,record-impl = /bits/ 64 <0x3>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,processor-flags = ; ++ arm,resource-type = ; ++ interrupts = ; ++ interrupt-names = "fhi"; ++ }; ++ ++ /* Memory-mapped memory controller error source */ ++ aest-memory-0@50010000 { ++ compatible = "arm,aest-memory"; ++ reg = <0x0 0x50010000 0x0 0x1000>, ++ <0x0 0x50011000 0x0 0x1000>, ++ <0x0 0x50012000 0x0 0x1000>; ++ reg-names = "err-group", "fault-inject", "irq-config"; ++ arm,group-format = ; ++ arm,num-records = <4>; ++ arm,record-impl = /bits/ 64 <0xf>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,interface-flags = ; ++ arm,proximity-domain = <0>; ++ interrupts = , ++ ; ++ interrupt-names = "fhi", "eri"; ++ }; ++ }; +diff --git a/include/dt-bindings/arm/aest.h b/include/dt-bindings/arm/aest.h +new file mode 100644 +index 000000000000..43679314e98e +--- /dev/null ++++ b/include/dt-bindings/arm/aest.h +@@ -0,0 +1,43 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * This header provides constants for the Arm Error Source Table (AEST) ++ * DT binding (Documentation/devicetree/bindings/arm/arm,aest.yaml). ++ */ ++ ++#ifndef _DT_BINDINGS_ARM_AEST_H ++#define _DT_BINDINGS_ARM_AEST_H ++ ++/* arm,interface-flags - AEST node interface flags field */ ++#define AEST_XFACE_SHARED 1 ++#define AEST_XFACE_CLEAR_MISC 2 ++#define AEST_XFACE_ERROR_DEVICE 4 ++#define AEST_XFACE_AFFINITY 8 ++#define AEST_XFACE_ERROR_GROUP 16 ++#define AEST_XFACE_FAULT_INJECT 32 ++#define AEST_XFACE_INT_CONFIG 64 ++ ++/* arm,fhi-flags / arm,eri-flags - AEST node interrupt flags field */ ++#define AEST_IRQ_MODE_LEVEL 0 ++#define AEST_IRQ_MODE_EDGE 1 ++ ++/* arm,processor-flags - AEST processor node flags field */ ++#define AEST_PROC_GLOBAL 1 ++#define AEST_PROC_SHARED 2 ++ ++/* arm,group-format - error record group register window page size */ ++#define AEST_GROUP_FORMAT_4K 0 ++#define AEST_GROUP_FORMAT_16K 1 ++#define AEST_GROUP_FORMAT_64K 2 ++ ++/* arm,resource-type - processor resource type */ ++#define AEST_RESOURCE_CACHE 0 ++#define AEST_RESOURCE_TLB 1 ++#define AEST_RESOURCE_GENERIC 2 ++ ++/* arm,gic-type - GIC component type */ ++#define AEST_GIC_CPU 0 ++#define AEST_GIC_DISTRIBUTOR 1 ++#define AEST_GIC_REDISTRIBUTOR 2 ++#define AEST_GIC_ITS 3 ++ ++#endif /* _DT_BINDINGS_ARM_AEST_H */ + +-- +2.34.1 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB8DD428463 + for ; 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It is +initialized at the same layer as ACPI and is mutually exclusive with it, +ensuring identical behaviour regardless of the firmware interface in use. + +Signed-off-by: Umang Chheda +--- + drivers/ras/aest/Kconfig | 15 +- + drivers/ras/aest/Makefile | 2 + + drivers/ras/aest/aest-of.c | 673 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 688 insertions(+), 2 deletions(-) + +diff --git a/drivers/ras/aest/Kconfig b/drivers/ras/aest/Kconfig +index 0b09a5d5acce..ca034255fadd 100644 +--- a/drivers/ras/aest/Kconfig ++++ b/drivers/ras/aest/Kconfig +@@ -7,11 +7,22 @@ + + config AEST + tristate "ARM AEST Driver" +- depends on ACPI_AEST && RAS +- ++ depends on ACPI_AEST || OF_AEST ++ depends on RAS + help + The Arm Error Source Table (AEST) provides details on ACPI + extensions that enable kernel-first handling of errors in a + system that supports the Armv8 RAS extensions. + + If set, the kernel will report and log hardware errors. ++ ++config OF_AEST ++ bool "ARM Error Source Table DT Support" ++ depends on ARM64_RAS_EXTN && OF ++ help ++ Enable support for discovering ARM RAS error sources using the ++ Device Tree based Arm Error Source Table (AEST) specification. ++ This allows the kernel to enumerate and manage hardware error ++ reporting blocks described in firmware for ARMv8 and later ++ systems. Select this option if your platform describes AEST ++ nodes in Device Tree and relies on RAS error handling. +diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile +index e5a45fde6d36..2997952901c0 100644 +--- a/drivers/ras/aest/Makefile ++++ b/drivers/ras/aest/Makefile +@@ -6,3 +6,5 @@ aest-y := aest-core.o + aest-y += aest-sysfs.o + aest-y += aest-inject.o + aest-y += aest-cmn.o ++ ++obj-$(CONFIG_OF_AEST) += aest-of.o +diff --git a/drivers/ras/aest/aest-of.c b/drivers/ras/aest/aest-of.c +new file mode 100644 +index 000000000000..939db2c41742 +--- /dev/null ++++ b/drivers/ras/aest/aest-of.c +@@ -0,0 +1,673 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#undef pr_fmt ++#define pr_fmt(fmt) "DT AEST: " fmt ++ ++struct dt_aest_priv { ++ struct xarray aest_array; ++ u32 node_id; ++}; ++ ++static const struct of_device_id dt_aest_child_match[] = { ++ { .compatible = "arm,aest-processor", .data = (void *)ACPI_AEST_PROCESSOR_ERROR_NODE }, ++ { .compatible = "arm,aest-memory", .data = (void *)ACPI_AEST_MEMORY_ERROR_NODE }, ++ { .compatible = "arm,aest-smmu", .data = (void *)ACPI_AEST_SMMU_ERROR_NODE }, ++ { .compatible = "arm,aest-vendor", .data = (void *)ACPI_AEST_VENDOR_ERROR_NODE }, ++ { .compatible = "arm,aest-gic", .data = (void *)ACPI_AEST_GIC_ERROR_NODE }, ++ { .compatible = "arm,aest-pcie", .data = (void *)ACPI_AEST_PCIE_ERROR_NODE }, ++ { .compatible = "arm,aest-proxy", .data = (void *)ACPI_AEST_PROXY_ERROR_NODE }, ++ { } ++}; ++ ++static int dt_aest_node_type(struct device_node *np) ++{ ++ const struct of_device_id *match; ++ ++ match = of_match_node(dt_aest_child_match, np); ++ if (!match) { ++ pr_warn("unknown compatible for %pOF\n", np); ++ return -EINVAL; ++ } ++ return (int)(uintptr_t)match->data; ++} ++ ++static struct aest_hnode *dt_aest_alloc_hnode(int node_type, u32 id) ++{ ++ struct aest_hnode *ahnode; ++ ++ ahnode = kzalloc_obj(*ahnode, GFP_KERNEL); ++ if (!ahnode) ++ return NULL; ++ ++ INIT_LIST_HEAD(&ahnode->list); ++ ahnode->count = 0; ++ ahnode->id = id; ++ ahnode->type = node_type; ++ return ahnode; ++} ++ ++static int dt_aest_build_interface(struct device_node *np, ++ struct acpi_aest_node *anode) ++{ ++ struct acpi_aest_node_interface_header *hdr; ++ struct acpi_aest_node_interface_common *common; ++ struct resource res; ++ struct resource named_res; ++ u32 gfmt = 0, flags = 0, nrec = 1; ++ u32 itype; ++ int ret; ++ size_t body_sz; ++ ++ /* ++ * Deduce interface type from the presence and count of reg entries: ++ * no reg -> system-register access (type 0) ++ * 1 range -> memory-mapped access (type 1) ++ * 2+ ranges -> single-record MMIO (type 2) ++ */ ++ if (!of_property_present(np, "reg")) ++ itype = ACPI_AEST_NODE_SYSTEM_REGISTER; ++ else if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) <= ++ (of_n_addr_cells(np) + of_n_size_cells(np))) ++ itype = ACPI_AEST_NODE_MEMORY_MAPPED; ++ else ++ itype = ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED; ++ ++ of_property_read_u32(np, "arm,group-format", &gfmt); ++ of_property_read_u32(np, "arm,interface-flags", &flags); ++ of_property_read_u32(np, "arm,num-records", &nrec); ++ ++ switch (gfmt) { ++ case ACPI_AEST_NODE_GROUP_FORMAT_16K: ++ body_sz = sizeof(struct acpi_aest_node_interface_16k); ++ break; ++ case ACPI_AEST_NODE_GROUP_FORMAT_64K: ++ body_sz = sizeof(struct acpi_aest_node_interface_64k); ++ break; ++ default: ++ body_sz = sizeof(struct acpi_aest_node_interface_4k); ++ break; ++ } ++ ++ hdr = kzalloc(sizeof(*hdr) + body_sz, GFP_KERNEL); ++ if (!hdr) ++ return -ENOMEM; ++ ++ /* Fill header */ ++ hdr->type = (u8)itype; ++ hdr->group_format = (u8)gfmt; ++ hdr->flags = flags; ++ hdr->error_record_count = nrec; ++ hdr->error_record_index = 0; ++ ++ if (itype != ACPI_AEST_NODE_SYSTEM_REGISTER) { ++ ret = of_address_to_resource(np, 0, &res); ++ if (ret) { ++ pr_err("node %pOF: missing 'reg' for MMIO interface\n", np); ++ kfree(hdr); ++ return ret; ++ } ++ hdr->address = res.start; ++ } ++ ++ switch (gfmt) { ++ case ACPI_AEST_NODE_GROUP_FORMAT_4K: { ++ struct acpi_aest_node_interface_4k *b = ++ (struct acpi_aest_node_interface_4k *)(hdr + 1); ++ of_property_read_u64(np, "arm,record-impl", ++ &b->error_record_implemented); ++ of_property_read_u64(np, "arm,status-reporting", ++ &b->error_status_reporting); ++ of_property_read_u64(np, "arm,addressing-mode", ++ &b->addressing_mode); ++ common = &b->common; ++ anode->record_implemented = ++ (unsigned long *)&b->error_record_implemented; ++ anode->status_reporting = ++ (unsigned long *)&b->error_status_reporting; ++ anode->addressing_mode = ++ (unsigned long *)&b->addressing_mode; ++ break; ++ } ++ case ACPI_AEST_NODE_GROUP_FORMAT_16K: { ++ struct acpi_aest_node_interface_16k *b = ++ (struct acpi_aest_node_interface_16k *)(hdr + 1); ++ of_property_read_u64_array(np, "arm,record-impl", ++ b->error_record_implemented, 4); ++ of_property_read_u64_array(np, "arm,status-reporting", ++ b->error_status_reporting, 4); ++ of_property_read_u64_array(np, "arm,addressing-mode", ++ b->addressing_mode, 4); ++ common = &b->common; ++ anode->record_implemented = ++ (unsigned long *)b->error_record_implemented; ++ anode->status_reporting = ++ (unsigned long *)b->error_status_reporting; ++ anode->addressing_mode = ++ (unsigned long *)b->addressing_mode; ++ break; ++ } ++ case ACPI_AEST_NODE_GROUP_FORMAT_64K: { ++ struct acpi_aest_node_interface_64k *b = ++ (struct acpi_aest_node_interface_64k *)(hdr + 1); ++ of_property_read_u64_array(np, "arm,record-impl", ++ b->error_record_implemented, 14); ++ of_property_read_u64_array(np, "arm,status-reporting", ++ b->error_status_reporting, 14); ++ of_property_read_u64_array(np, "arm,addressing-mode", ++ b->addressing_mode, 14); ++ common = &b->common; ++ anode->record_implemented = ++ (unsigned long *)b->error_record_implemented; ++ anode->status_reporting = ++ (unsigned long *)b->error_status_reporting; ++ anode->addressing_mode = ++ (unsigned long *)b->addressing_mode; ++ break; ++ } ++ default: ++ pr_err("node %pOF: unsupported group-format %u\n", np, gfmt); ++ kfree(hdr); ++ return -EINVAL; ++ } ++ ++ if (!of_address_to_resource(np, of_property_match_string( ++ np, "reg-names", "fault-inject"), &named_res)) ++ common->fault_inject_register_base = named_res.start; ++ ++ if (!of_address_to_resource(np, of_property_match_string( ++ np, "reg-names", "err-group"), &named_res)) ++ common->error_group_register_base = named_res.start; ++ ++ if (!of_address_to_resource(np, of_property_match_string( ++ np, "reg-names", "irq-config"), &named_res)) ++ common->interrupt_config_register_base = named_res.start; ++ ++ anode->interface_hdr = hdr; ++ anode->common = common; ++ ++ return 0; ++} ++ ++static int dt_aest_build_interrupt(struct device_node *np, ++ struct acpi_aest_node *anode) ++{ ++ struct acpi_aest_node_interrupt_v2 *irq_arr; ++ int fhi_irq, eri_irq, count = 0; ++ u32 fhi_flags = 0, eri_flags = 0; ++ ++ of_property_read_u32(np, "arm,fhi-flags", &fhi_flags); ++ of_property_read_u32(np, "arm,eri-flags", &eri_flags); ++ ++ fhi_irq = of_irq_get_byname(np, "fhi"); ++ if (fhi_irq == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ if (fhi_irq < 0 && fhi_irq != -EINVAL) { ++ const char *name = NULL; ++ ++ of_property_read_string(np, "interrupt-names", &name); ++ ++ pr_warn("node %pOF: failed to map FHI IRQ: %d (interrupt-names[0]=\"%s\", want \"%s\")\n", ++ np, fhi_irq, name ?: "", "fhi"); ++ } ++ eri_irq = of_irq_get_byname(np, "eri"); ++ if (eri_irq == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ if (eri_irq < 0 && eri_irq != -EINVAL) { ++ const char *name = NULL; ++ ++ of_property_read_string_index(np, "interrupt-names", 1, &name); ++ ++ pr_warn("node %pOF: failed to map ERI IRQ: %d (interrupt-names[1]=\"%s\", want \"%s\")\n", ++ np, eri_irq, name ?: "", "eri"); ++ } ++ ++ if (fhi_irq > 0) ++ count++; ++ if (eri_irq > 0) ++ count++; ++ ++ if (!count) { ++ anode->interrupt = NULL; ++ anode->interrupt_count = 0; ++ return 0; ++ } ++ ++ irq_arr = kcalloc(count, sizeof(*irq_arr), GFP_KERNEL); ++ if (!irq_arr) ++ return -ENOMEM; ++ ++ count = 0; ++ if (fhi_irq > 0) { ++ irq_arr[count].gsiv = fhi_irq; ++ irq_arr[count].flags = AEST_INTERRUPT_MODE | fhi_flags; ++ irq_arr[count].type = ACPI_AEST_NODE_FAULT_HANDLING; ++ count++; ++ } ++ if (eri_irq > 0) { ++ irq_arr[count].gsiv = eri_irq; ++ irq_arr[count].flags = eri_flags; ++ irq_arr[count].type = ACPI_AEST_NODE_ERROR_RECOVERY; ++ count++; ++ } ++ ++ anode->interrupt = irq_arr; ++ anode->interrupt_count = count; ++ return 0; ++} ++ ++static int dt_aest_build_node_specific(struct device_node *np, ++ struct acpi_aest_node *anode, ++ int node_type) ++{ ++ switch (node_type) { ++ ++ case ACPI_AEST_PROCESSOR_ERROR_NODE: { ++ struct acpi_aest_processor *proc; ++ u32 rtype = 0, pflags = 0; ++ ++ proc = kzalloc_obj(*proc, GFP_KERNEL); ++ if (!proc) ++ return -ENOMEM; ++ ++ of_property_read_u32(np, "arm,resource-type", &rtype); ++ of_property_read_u32(np, "arm,processor-flags", &pflags); ++ ++ proc->resource_type = (u8)rtype; ++ proc->flags = (u8)pflags; ++ ++ /* Processor cache/TLB/generic sub-structure */ ++ switch (rtype) { ++ case ACPI_AEST_CACHE_RESOURCE: { ++ struct acpi_aest_processor_cache *c; ++ struct device_node *cache_np; ++ ++ c = kzalloc_obj(*c, GFP_KERNEL); ++ if (!c) { ++ kfree(proc); ++ return -ENOMEM; ++ } ++ ++ cache_np = of_parse_phandle(np, "arm,cache-ref", 0); ++ if (cache_np) { ++ c->cache_reference = cache_np->phandle; ++ of_node_put(cache_np); ++ } ++ anode->cache = c; ++ break; ++ } ++ case ACPI_AEST_TLB_RESOURCE: { ++ struct acpi_aest_processor_tlb *t; ++ ++ t = kzalloc_obj(*t, GFP_KERNEL); ++ if (!t) { ++ kfree(proc); ++ return -ENOMEM; ++ } ++ of_property_read_u32(np, "arm,tlb-level", ++ &t->tlb_level); ++ anode->tlb = t; ++ break; ++ } ++ default: { ++ struct acpi_aest_processor_generic *g; ++ ++ g = kzalloc_obj(*g, GFP_KERNEL); ++ if (!g) { ++ kfree(proc); ++ return -ENOMEM; ++ } ++ of_property_read_u32(np, "arm,resource-ref", ++ &g->resource); ++ anode->generic = g; ++ break; ++ } ++ } ++ anode->processor = proc; ++ break; ++ } ++ ++ case ACPI_AEST_MEMORY_ERROR_NODE: { ++ struct acpi_aest_memory *mem; ++ ++ mem = kzalloc_obj(*mem, GFP_KERNEL); ++ ++ if (!mem) ++ return -ENOMEM; ++ of_property_read_u32(np, "arm,proximity-domain", ++ &mem->srat_proximity_domain); ++ anode->memory = mem; ++ break; ++ } ++ ++ case ACPI_AEST_SMMU_ERROR_NODE: { ++ struct acpi_aest_smmu *smmu; ++ struct device_node *smmu_np; ++ ++ smmu = kzalloc_obj(*smmu, GFP_KERNEL); ++ ++ if (!smmu) ++ return -ENOMEM; ++ smmu_np = of_parse_phandle(np, "arm,smmu-ref", 0); ++ if (smmu_np) { ++ /* Use the DT node offset as the IORT reference */ ++ smmu->iort_node_reference = smmu_np->phandle; ++ of_node_put(smmu_np); ++ } ++ of_property_read_u32(np, "arm,smmu-subcomponent", ++ &smmu->subcomponent_reference); ++ anode->smmu = smmu; ++ break; ++ } ++ ++ case ACPI_AEST_VENDOR_ERROR_NODE: { ++ struct acpi_aest_vendor_v2 *vendor; ++ const char *hid = "ARMHC000"; ++ ++ vendor = kzalloc_obj(*vendor, GFP_KERNEL); ++ ++ if (!vendor) ++ return -ENOMEM; ++ of_property_read_string(np, "arm,vendor-hid", &hid); ++ strscpy(vendor->acpi_hid, hid, sizeof(vendor->acpi_hid)); ++ of_property_read_u32(np, "arm,vendor-uid", ++ &vendor->acpi_uid); ++ anode->vendor = vendor; ++ break; ++ } ++ ++ case ACPI_AEST_GIC_ERROR_NODE: { ++ struct acpi_aest_gic *gic; ++ ++ gic = kzalloc_obj(*gic, GFP_KERNEL); ++ ++ if (!gic) ++ return -ENOMEM; ++ of_property_read_u32(np, "arm,gic-type", ++ &gic->interface_type); ++ of_property_read_u32(np, "arm,gic-instance", ++ &gic->instance_id); ++ anode->gic = gic; ++ break; ++ } ++ ++ case ACPI_AEST_PCIE_ERROR_NODE: { ++ struct acpi_aest_pcie *pcie; ++ ++ pcie = kzalloc_obj(*pcie, GFP_KERNEL); ++ ++ if (!pcie) ++ return -ENOMEM; ++ of_property_read_u32(np, "arm,pcie-segment", ++ &pcie->iort_node_reference); ++ anode->pcie = pcie; ++ break; ++ } ++ ++ case ACPI_AEST_PROXY_ERROR_NODE: ++ /* No node-specific data for proxy nodes */ ++ anode->spec_pointer = NULL; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static struct acpi_aest_node * ++dt_aest_alloc_anode(struct device_node *np, int node_type) ++{ ++ struct acpi_aest_node *anode; ++ int ret; ++ ++ anode = kzalloc_obj(*anode, GFP_KERNEL); ++ if (!anode) ++ return ERR_PTR(-ENOMEM); ++ ++ INIT_LIST_HEAD(&anode->list); ++ anode->type = node_type; ++ ++ ret = dt_aest_build_interface(np, anode); ++ if (ret) ++ goto err_free; ++ ++ ret = dt_aest_build_node_specific(np, anode, node_type); ++ if (ret) ++ goto err_free; ++ ++ ret = dt_aest_build_interrupt(np, anode); ++ if (ret) ++ goto err_free; ++ ++ return anode; ++ ++err_free: ++ kfree(anode->interface_hdr); ++ kfree(anode->spec_pointer); ++ kfree(anode->processor_spec_pointer); ++ kfree(anode); ++ return ERR_PTR(ret); ++} ++ ++static int dt_aest_init_one_node(struct device_node *np, ++ struct dt_aest_priv *priv) ++{ ++ int node_type; ++ struct aest_hnode *ahnode; ++ struct acpi_aest_node *anode; ++ ++ node_type = dt_aest_node_type(np); ++ if (node_type < 0) { ++ pr_warn("unknown node type for %pOF, skipping\n", np); ++ return 0; ++ } ++ ++ ahnode = dt_aest_alloc_hnode(node_type, priv->node_id); ++ if (!ahnode) ++ return -ENOMEM; ++ ++ anode = dt_aest_alloc_anode(np, node_type); ++ if (IS_ERR(anode)) { ++ kfree(ahnode); ++ return PTR_ERR(anode); ++ } ++ ++ list_add_tail(&anode->list, &ahnode->list); ++ ahnode->count = 1; ++ ++ if (xa_err(xa_store(&priv->aest_array, priv->node_id, ++ ahnode, GFP_KERNEL))) { ++ kfree(anode); ++ kfree(ahnode); ++ return -ENOMEM; ++ } ++ priv->node_id++; ++ return 0; ++} ++ ++static int dt_aest_init_nodes(struct device_node *aest_root, ++ struct dt_aest_priv *priv) ++{ ++ struct device_node *np; ++ int ret; ++ ++ for_each_available_child_of_node(aest_root, np) { ++ ret = dt_aest_init_one_node(np, priv); ++ if (ret) { ++ pr_err("failed to init node %pOF: %d\n", np, ret); ++ of_node_put(np); ++ return ret; ++ } ++ } ++ return 0; ++} ++ ++static struct platform_device *dt_aest_alloc_pdev(struct aest_hnode *ahnode, ++ int index) ++{ ++ struct platform_device *pdev; ++ struct resource *res; ++ struct acpi_aest_node *anode; ++ int ret, size, j; ++ int irq[AEST_MAX_INTERRUPT_PER_NODE] = { 0 }; ++ ++ pdev = platform_device_alloc("AEST", index); ++ if (!pdev) ++ return ERR_PTR(-ENOMEM); ++ ++ res = kcalloc(ahnode->count + AEST_MAX_INTERRUPT_PER_NODE, ++ sizeof(*res), GFP_KERNEL); ++ if (!res) { ++ platform_device_put(pdev); ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ j = 0; ++ list_for_each_entry(anode, &ahnode->list, list) { ++ if (anode->interface_hdr->type != ++ ACPI_AEST_NODE_SYSTEM_REGISTER) { ++ res[j].name = AEST_NODE_NAME; ++ res[j].start = anode->interface_hdr->address; ++ ++ switch (anode->interface_hdr->group_format) { ++ case ACPI_AEST_NODE_GROUP_FORMAT_4K: ++ size = 4 * KB; break; ++ case ACPI_AEST_NODE_GROUP_FORMAT_16K: ++ size = 16 * KB; break; ++ case ACPI_AEST_NODE_GROUP_FORMAT_64K: ++ size = 64 * KB; break; ++ default: ++ size = 4 * KB; ++ } ++ res[j].end = res[j].start + size - 1; ++ res[j].flags = IORESOURCE_MEM; ++ j++; ++ } ++ ++ if (anode->interrupt && anode->interrupt_count > 0) { ++ int k; ++ ++ for (k = 0; k < anode->interrupt_count && ++ k < AEST_MAX_INTERRUPT_PER_NODE; k++) { ++ ++ struct acpi_aest_node_interrupt_v2 *intr = ++ &anode->interrupt[k]; ++ int itype = intr->type; ++ int virq = intr->gsiv; ++ struct irq_data *irqd; ++ ++ if (!virq) ++ continue; ++ if (itype >= AEST_MAX_INTERRUPT_PER_NODE) ++ continue; ++ if (irq[itype] == virq) ++ continue; ++ irq[itype] = virq; ++ /* ++ * aest_config_irq() writes intr->gsiv directly ++ * to the hardware IRQ-config register, so it ++ * must hold the GIC hardware SPI number, not the ++ * Linux virtual IRQ. Convert here now that we ++ * have the virq in hand; the resource still gets ++ * the virq so devm_request_irq() works correctly. ++ */ ++ irqd = irq_get_irq_data(virq); ++ if (irqd) ++ intr->gsiv = irqd->hwirq; ++ ++ res[j].name = (itype == ACPI_AEST_NODE_FAULT_HANDLING) ++ ? AEST_FHI_NAME : AEST_ERI_NAME; ++ res[j].start = virq; ++ res[j].end = virq; ++ res[j].flags = IORESOURCE_IRQ; ++ j++; ++ } ++ } ++ } ++ ++ ret = platform_device_add_resources(pdev, res, j); ++ kfree(res); ++ if (ret) { ++ platform_device_put(pdev); ++ return ERR_PTR(ret); ++ } ++ ++ ret = platform_device_add_data(pdev, &ahnode, sizeof(ahnode)); ++ if (ret) { ++ platform_device_put(pdev); ++ return ERR_PTR(ret); ++ } ++ ++ ret = platform_device_add(pdev); ++ if (ret) { ++ platform_device_put(pdev); ++ return ERR_PTR(ret); ++ } ++ ++ return pdev; ++} ++ ++static int dt_aest_alloc_pdevs(struct dt_aest_priv *priv) ++{ ++ struct aest_hnode *ahnode; ++ unsigned long i; ++ int ret = 0, index = 0; ++ ++ xa_for_each(&priv->aest_array, i, ahnode) { ++ struct platform_device *pdev = ++ dt_aest_alloc_pdev(ahnode, index++); ++ if (IS_ERR(pdev)) { ++ ret = PTR_ERR(pdev); ++ pr_err("failed to alloc pdev for node %u: %d\n", ++ ahnode->id, ret); ++ break; ++ } ++ } ++ return ret; ++} ++ ++static int __init dt_aest_init(void) ++{ ++ struct device_node *aest_root; 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These nodes model the +hardware error reporting blocks and associated interrupts as required +by the Arm AEST specification. + +Co-developed-by: Faruque Ansari +Signed-off-by: Faruque Ansari +Signed-off-by: Umang Chheda +--- + arch/arm64/boot/dts/qcom/lemans.dtsi | 41 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi +index fe6e76351823..199ea1f9a8d5 100644 +--- a/arch/arm64/boot/dts/qcom/lemans.dtsi ++++ b/arch/arm64/boot/dts/qcom/lemans.dtsi +@@ -4,6 +4,7 @@ + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + ++#include + #include + #include + #include +@@ -29,6 +30,46 @@ / { + #address-cells = <2>; + #size-cells = <2>; + ++ aest { ++ compatible = "arm,aest"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ aest-processor-0 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <1>; ++ arm,record-impl = /bits/ 64 <0x0>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,processor-flags = ; ++ interrupts = ; ++ interrupt-names = "fhi"; ++ }; ++ ++ aest-l3-cluster0 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <2>; ++ arm,record-impl = /bits/ 64 <0x1>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,processor-flags = ; ++ interrupts = ; ++ interrupt-names = "fhi"; ++ }; ++ ++ aest-l3-cluster1 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <2>; ++ arm,record-impl = /bits/ 64 <0x1>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; 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These nodes model the +hardware error reporting blocks and associated interrupts as required +by the Arm AEST specification. + +Co-developed-by: Faruque Ansari +Signed-off-by: Faruque Ansari +Signed-off-by: Umang Chheda +--- + arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi +index 7b1d57460f1e..8e43ceed7d84 100644 +--- a/arch/arm64/boot/dts/qcom/monaco.dtsi ++++ b/arch/arm64/boot/dts/qcom/monaco.dtsi +@@ -3,6 +3,7 @@ + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + ++#include + #include + #include + #include +@@ -29,6 +30,46 @@ / { + #address-cells = <2>; + #size-cells = <2>; + ++ aest { ++ compatible = "arm,aest"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ aest-processor-0 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <1>; ++ arm,record-impl = /bits/ 64 <0x0>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,processor-flags = ; ++ interrupts = ; ++ interrupt-names = "fhi"; ++ }; ++ ++ aest-l3-cluster0 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <2>; ++ arm,record-impl = /bits/ 64 <0x1>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,processor-flags = ; ++ interrupts = ; ++ interrupt-names = "fhi"; ++ }; ++ ++ aest-l3-cluster1 { ++ compatible = "arm,aest-processor"; ++ arm,num-records = <2>; ++ arm,record-impl = /bits/ 64 <0x1>; ++ arm,status-reporting = /bits/ 64 <0x0>; ++ arm,addressing-mode = /bits/ 64 <0x0>; ++ arm,processor-flags = ; ++ interrupts = ; ++ interrupt-names = "fhi"; ++ }; ++ }; ++ + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + +-- +2.34.1 + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id A25EE29AAFD; + Wed, 6 May 2026 08:07:05 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.132 +ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; + t=1778054830; cv=none; b=Zbs0ePQ5EBq7OlHBEyM/kkgiItiDT2Ncd8VVZ5ynlk3jhL3mDyTikl3p/N7cefTzCyh6YZw87R6Ax1Qv4cY0CyK76QcrPYgt3jRTE5BShxZIsibkVtwSJRduNmkv017GTiWc0H7D6T0HSJJ7NQUVwMkU67gv6R0Gped0wxNTWVo= +ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; + s=arc-20240116; t=1778054830; c=relaxed/simple; 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charset=UTF-8; format=flowed +Content-Transfer-Encoding: 8bit + + + +在 2026/5/5 20:23, Umang Chheda 写道: +> The driver unconditionally calls panic() whenever an unrecoverable, +> uncontainable UE (UET_UC or UET_UEU) is detected. There is no way +> for the user to suppress this behaviour, which makes it difficult to +> test UE injection or to run in environments where a kernel panic on +> every UE is undesirable. +> +> Add a module parameter `aest_panic_on_ue` When set to 0 the driver +> logs the UE and continues instead of panicking. +> +> Usage: +> # Boot time (kernel cmdline) +> aest.aest_panic_on_ue=0 +> +> # Runtime +> echo 0 > /sys/module/aest/parameters/aest_panic_on_ue +> +> Signed-off-by: Umang Chheda + +Hi Umang, + +Thanks for the patch. + +I understand that this parameter is intended to facilitate UE injection +testing and to avoid kernel panics in certain environments. However, we +need to carefully consider the potential risks. + +When a UC (Uncontainable Error) or UEU (Unrecoverable Error) occurs, the +hardware state may be unpredictable, and data integrity cannot be +guaranteed. Allowing the system to continue running instead of panicking +in these scenarios could lead to silent data corruption or other +unforeseen side effects, which poses a significant risk to system stability. + +For the sake of robustness and data safety, I do not believe we should +expose an interface that allows users to suppress panic on such critical +errors. + +If the goal is primarily to ease testing, I suggest handling this via +local driver modifications in your test environment rather than +upstreaming it as a configurable runtime option. + +Best regards, +Ruidong + +> --- +> drivers/ras/aest/aest-core.c | 9 ++++++++- +> 1 file changed, 8 insertions(+), 1 deletion(-) +> +> diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c +> index b4f4c975da1d..9ce782a66edf 100644 +> --- a/drivers/ras/aest/aest-core.c +> +++ b/drivers/ras/aest/aest-core.c +> @@ -22,6 +22,11 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); +> #undef pr_fmt +> #define pr_fmt(fmt) "AEST: " fmt +> +> +static bool aest_panic_on_ue; +> +module_param(aest_panic_on_ue, bool, 0644); +> +MODULE_PARM_DESC(aest_panic_on_ue, +> + "Panic on unrecoverable error: 0=off 1=on (default: 1)"); +> + +> #ifdef CONFIG_DEBUG_FS +> struct dentry *aest_debugfs; +> #endif +> @@ -342,9 +347,11 @@ void aest_proc_record(struct aest_record *record, void *data, bool fake) +> aest_record_info( +> record, +> "Simulated error! Skip panic due to fault injection\n"); +> - else +> + else if (aest_panic_on_ue) +> aest_panic(record, ®s, +> "AEST: unrecoverable error encountered"); +> + else +> + aest_record_err(record, "UE detected, panic suppressed\n"); +> } +> +> aest_log(record, ®s); +> + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88CB217A300; + Wed, 6 May 2026 08:10:21 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 +ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; + t=1778055024; cv=none; b=uA3ZiOdVQbja/RJzF60GG1RtdyWBAqj4oRi001iMiJ2+Fe3TmVVTT4RjE8MlsB6wIYg4OR0AHvSeEX0Auq9bUcGLUoQp61bOfo7RLOHEla90nR7t9afa/IOUFCN+XXGIXwHHeWtCfg1dMKEcfmMlO0UlptAZEkkogzwRqvDkBDE= +ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; + s=arc-20240116; t=1778055024; c=relaxed/simple; + bh=+4EHq0NHNjFiTqj7OpA8rCswRIBR6KQes6hTJINDKBk=; + h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: + In-Reply-To:Content-Type; b=J+gdbWVsZ/YNFxEgMWYWp73BpYKQHMWPAKryXZbNHhxpm46TkCoVnPyLYQLJEl/H99qaHaMU0QBtot2QQtsTX4TAIph3p6JJLGU2K1MPPKSAbEX90/9WykN7QMXsnvPPOjnG9nCSpjuo/pDXAEynT3vvfOdjbQ4TZaZcGuR0AQo= +ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=j+v1r4ei; arc=none smtp.client-ip=115.124.30.100 +Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com +Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com +Authentication-Results: smtp.subspace.kernel.org; + dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="j+v1r4ei" +DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; + d=linux.alibaba.com; s=default; + t=1778055013; h=Message-ID:Date:MIME-Version:Subject:To:From:Content-Type; + bh=yA4Q4VrBxQuoKXsSh7fBnRgwqj5jLm5OpfFWZ/Xem1k=; + b=j+v1r4eik7V1y0n0NDFzDWf/naXSYA4F13bJNoxEbqmzTTwl0jGUUTcOpDqICCFvyIFKKUzsTK8rc2KjeeWcKLpy8DhnEluoKpzfQ2cjCkpH/r8N3Pao/NvVODhmclSQZIS/Vj+1sdrr9zKKOdQ1X8W8JCj5GjdphwYOoGMx5Oc= +X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R191e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=tianruidong@linux.alibaba.com;NM=1;PH=DS;RN=22;SR=0;TI=SMTPD_---0X2NUGIF_1778055011; +Received: from 30.221.149.96(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0X2NUGIF_1778055011 cluster:ay36) + by smtp.aliyun-inc.com; + Wed, 06 May 2026 16:10:12 +0800 +Message-ID: <8f1529af-f6fe-44bc-a4b1-c47a19824d1e@linux.alibaba.com> +Date: Wed, 6 May 2026 16:10:11 +0800 +Precedence: bulk +X-Mailing-List: linux-kernel@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +User-Agent: Mozilla Thunderbird +Subject: Re: [PATCH 0/8] ras: aest: extend AEST support to Device Tree + frontend +To: Umang Chheda , + Ruidong Tian , Tony Luck + , Borislav Petkov , + Rob Herring , Krzysztof Kozlowski , + Conor Dooley , Bjorn Andersson , + Konrad Dybcio , catalin.marinas@arm.com, + will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, + mark.rutland@arm.com, Sudeep Holla +Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, + linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, + Faruque Ansari +References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> +From: Ruidong Tian +In-Reply-To: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> +Content-Type: text/plain; charset=UTF-8; format=flowed +Content-Transfer-Encoding: 8bit + +Hi Umang, + +Thanks for your patch. + +Would it be okay if I include this patch in the next version of the AEST +patch series? I will make sure to add your Signed-off-by line. + +Best regards, +Ruidong + +在 2026/5/5 20:23, Umang Chheda 写道: +> This series extends Tian Ruidong’s [1] ACPI-based AEST support series +> to also cover Device Tree based platforms. +> +> While the existing AEST driver relies on the AEST ACPI table [3], many +> embedded Arm platforms use Device Tree exclusively and cannot use the +> driver today. This series adds a DT frontend that mirrors the ACPI +> implementation and feeds the same core driver, keeping ACPI and DT +> paths functionally equivalent. +> +> Along the way, several correctness issues were identified in the core +> driver and are fixed in the first part of this series. +> +> The DT frontend is mutually exclusive with ACPI and does not introduce +> any DT-specific logic into the core. +> +> How to test with QEMU +> -------------------------- +> Tian Ruidong's QEMU fork [2] emulates AEST MMIO error records on the +> virt machine. To test the DT frontend: +> +> 1. Build QEMU: +> +> git clone https://github.com/winterddd/qemu.git +> cd qemu +> git checkout c5e2d5dec9fd62ba622314c40bff0fbecb4dfb34 +> ./configure --target-list=aarch64-softmmu +> make -j$(nproc) +> +> 2. Build the kernel with: +> +> CONFIG_OF_AEST=y +> CONFIG_AEST=y +> CONFIG_ARM64_RAS_EXTN=y +> CONFIG_RAS=y +> +> 3. Add the following DT node to your virt machine DTB. The QEMU +> fork maps DRAM error records at 0x090d0000 (SPI 44) and CMN +> vendor records at 0x090e0000 (SPI 45): +> +> aest { +> compatible = "arm,aest"; +> #address-cells = <2>; +> #size-cells = <2>; +> ranges; +> interrupt-parent = <&gic>; +> +> /* DRAM memory node — MMIO at 0x090d0000, SPI 44 */ +> aest-dram0@90d0000 { +> compatible = "arm,aest-memory"; +> arm,interface-type = <1>; +> arm,group-format = <0>; +> arm,interface-flags = <0x22>; +> arm,num-records = <4>; +> arm,record-impl = /bits/ 64 <0x0>; +> arm,status-report = /bits/ 64 <0x0>; +> arm,addr-mode = /bits/ 64 <0x0>; +> arm,proximity-domain = <0>; +> reg = <0x0 0x090d0000 0x0 0x1000>, +> <0x0 0x090d0800 0x0 0x200>, +> <0x0 0x090d0e00 0x0 0x100>; +> reg-names = "errblock", "fault-inject", +> "err-group"; +> interrupts = ; +> interrupt-names = "fhi"; +> }; +> }; +> +> 4. Boot QEMU with acpi=off: +> +> ./qemu-system-aarch64 \ +> -machine virt,accel=tcg,gic-version=3 \ +> -cpu cortex-a57 -m 2G -smp 4 \ +> -kernel Image -dtb virt-aest.dtb \ +> -append "console=ttyAMA0 acpi=off earlycon" \ +> -nographic +> +> 5. Verify probe: +> +> dmesg | grep "DT AEST" +> # Expected: DT AEST: registered 1 AEST error source(s) from DT +> ls /sys/kernel/debug/aest/ +> +> 6. Inject a CE error via the QEMU MMIO fault injection registers. +> The QEMU device accepts 64-bit accesses only (use devmem with +> the 64-bit width flag): +> +> devmem 0x090d0808 64 0x80000040 # CDOFF | CE inject +> +> This triggers QEMU's error_record_inj_write() which sets +> ERRSTATUS.V=1 and asserts the IRQ. The kernel driver's +> aest_irq_func() fires, reads the status, and logs: +> +> AEST: {1}[Hardware Error]: Hardware error from AEST memory.90d0000 +> AEST: {1}[Hardware Error]: Error from memory at SRAT proximity domain 0x0 +> +> Testing +> ------- +> - Validated on Qualcomm's lemans-evk and monaco-evk board with DT boot. +> - Validated CE and UE injection via debugfs soft_inject. +> - Tested ACPI path is unaffected: ACPI boot continues to use +> drivers/acpi/arm64/aest.c unchanged. +> +> [1] https://lore.kernel.org/lkml/20260122094656.73399-1-tianruidong@linux.alibaba.com/ +> [2] https://github.com/winterddd/qemu/tree/error_record +> [3] https://developer.arm.com/documentation/den0085/0200/ +> +> Signed-off-by: Umang Chheda +> --- +> Umang Chheda (8): +> ras: aest: Fix shared processor node handling and error log messages +> ras: aest: Fix CE/UE error counts not incrementing in debugfs +> ras: aest: Skip unimplemented records in debugfs +> ras: aest: Add panic_on_ue module parameter +> dt-bindings: arm: ras: Introduce bindings for ARM AEST +> ras: aest: Add DT frontend for ARM AEST RAS error sources +> arm64: dts: qcom: lemans: add AEST error nodes +> arm64: dts: qcom: monaco: add AEST error nodes +> +> .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++ +> arch/arm64/boot/dts/qcom/lemans.dtsi | 41 ++ +> arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++ +> drivers/ras/aest/Kconfig | 15 +- +> drivers/ras/aest/Makefile | 2 + +> drivers/ras/aest/aest-core.c | 63 +- +> drivers/ras/aest/aest-of.c | 673 +++++++++++++++++++++ +> drivers/ras/aest/aest-sysfs.c | 27 +- +> drivers/ras/aest/aest.h | 15 +- +> include/dt-bindings/arm/aest.h | 43 ++ +> 10 files changed, 1310 insertions(+), 16 deletions(-) +> --- +> base-commit: a67b7fd0dd1f6ccf3d128dc2099cdb07af1f6a09 +> change-id: 20260505-aest-devicetree-support-a3722d90e1f5 +> prerequisite-message-id: <20260122094656.73399-1-tianruidong@linux.alibaba.com> +> prerequisite-patch-id: c5a7c6431c6c1e6351241e694ee053800039d41d +> prerequisite-patch-id: 1f6e2c20829eee41a210dd8a538f1e8efcc65872 +> prerequisite-patch-id: 5556287e3f46c2ed2c0431c53c7782e87bcbd866 +> prerequisite-patch-id: 2edae0a136d7779b8f686181720e71d044a73311 +> prerequisite-patch-id: b5190b2844dcb01e72f87a59f3a29548795fdb82 +> prerequisite-patch-id: 7ba848583708b2ae776a7ce847bb056e3de7f77b +> prerequisite-patch-id: 397e5b22802b67942435f4f2968f0b1e210ba0e8 +> prerequisite-patch-id: 2169f4b65537eecbd0ccbd2ad6b28c64ec44655d +> prerequisite-patch-id: b626f85d98747595b3240bc49e6ad9c9dd5c0fa9 +> prerequisite-patch-id: 1323dfd2eebad2ef6514dbbce58ba08e8859f894 +> prerequisite-patch-id: 95b826e5e329408437a3ef336c4f45d4d74f82bb +> prerequisite-patch-id: b60ff489a5a33c5d5220fa8144af7b7511769cba +> prerequisite-patch-id: 43f35a52b8a3d13c938ff08083403c1d3bd0df8b +> prerequisite-patch-id: c55d4e9117ca36d3c2cba82d550a618cb82bb745 +> prerequisite-patch-id: 3885e10f318ae8101d6909b35d92a976cc359e3c +> prerequisite-patch-id: 92958cde05577f069c5659018a274bb39cfb6b24 +> +> Best regards, +> -- +> Umang Chheda +> + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D6EC33F598 + for ; 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+ Mon, 11 May 2026 23:46:05 -0700 (PDT) +Received: from [10.92.198.185] ([202.46.23.19]) + by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1e847d0sm119936625ad.62.2026.05.11.23.45.57 + (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); + Mon, 11 May 2026 23:46:04 -0700 (PDT) +Message-ID: +Date: Tue, 12 May 2026 12:15:47 +0530 +Precedence: bulk +X-Mailing-List: linux-kernel@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +User-Agent: Mozilla Thunderbird +Subject: Re: [PATCH 0/8] ras: aest: extend AEST support to Device Tree + frontend +To: Ruidong Tian , + Tony Luck , Borislav Petkov , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Bjorn Andersson , + Konrad Dybcio , catalin.marinas@arm.com, + will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, + mark.rutland@arm.com, Sudeep Holla +Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, + linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, + Faruque Ansari +References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> + <8f1529af-f6fe-44bc-a4b1-c47a19824d1e@linux.alibaba.com> +Content-Language: en-US +From: Umang Chheda +In-Reply-To: <8f1529af-f6fe-44bc-a4b1-c47a19824d1e@linux.alibaba.com> +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +X-Proofpoint-ORIG-GUID: xUWqJfqpYhbaQPLlXqodY7Q3EyX8U0zK +X-Authority-Analysis: v=2.4 cv=CeM4Irrl c=1 sm=1 tr=0 ts=6a02ccaf cx=c_pps + a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 + a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 + a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 + a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=7CQSdrXTAAAA:8 a=SRrdq9N9AAAA:8 + a=EUspDBNiAAAA:8 a=2yO6rERebkD6Ods6SnIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 + a=GvdueXVYPmCkWapjIL-Q:22 a=a-qgeE7W1pNrGK8U0ZQC:22 +X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDA2NCBTYWx0ZWRfX7tp0Y0yZ3M5P + r605ipRqL4mphtD4mu4ia2STqndfnD+Etyo1/Mwf/FeaxRrRXSSqgcQiPnEwEdNdWAnV70yr5HN + 2OS0G3Mp6E5rUCFLd0PdYndiQ0xcb2vly2x065Ua539DtKW7hRchvkDq9Trn48ZrMQgkx20V16S + lyoglBaob4/QZ0mFptwn79k5vUD1OAv6gT5CMhs/B3QFUwp9H1j6W3lsQnZUve+LsQ4yd/sA9uW + Ur3ie61mfmMXr7xzsrbqk3qtj9IBusvG48XmG4T1cyCLIiKd4jzi6e2arWNWVnH7wVUhcv2HEPe + aqmF7Tm6K79vgr9sb4QPGNNfHacHeFVk4KQRhHCWujlZJarkc1IUQgh9IPEj8sMXNoCLmNsHmwx + 1+uQk4v1Z0aXOUTMFnisONGghK4MyenSm5KgNuYPq12igZpdRpUv+4ssI2uLz9eCdxmrURQHAQn + 7R8R5uVfVpsCYx3PkKw== +X-Proofpoint-GUID: xUWqJfqpYhbaQPLlXqodY7Q3EyX8U0zK +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 + definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + impostorscore=0 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 + clxscore=1015 lowpriorityscore=0 spamscore=0 adultscore=0 bulkscore=0 + classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 + reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120064 + +Hi Ruidong, + + +On 5/6/2026 1:40 PM, Ruidong Tian wrote: +> Hi Umang, +> +> Thanks for your patch. +> +> Would it be okay if I include this patch in the next version of the AEST +> patch series? I will make sure to add your Signed-off-by line. + + +Yes, you can include this patch in the next version - we will represent +it and respond to all of the queries received on DT specific patches. + +How should I be sharing the patch fixes based on comments received from +maintainers to you ? so that you can include in your patch series ? + +Also, when is your plan to post the next version fixing the comments +received ? + + +Thanks, +Umang + + +> +> Best regards, +> Ruidong +> +> 在 2026/5/5 20:23, Umang Chheda 写道: +>> This series extends Tian Ruidong’s [1] ACPI-based AEST support series +>> to also cover Device Tree based platforms. +>> +>> While the existing AEST driver relies on the AEST ACPI table [3], many +>> embedded Arm platforms use Device Tree exclusively and cannot use the +>> driver today. This series adds a DT frontend that mirrors the ACPI +>> implementation and feeds the same core driver, keeping ACPI and DT +>> paths functionally equivalent. +>> +>> Along the way, several correctness issues were identified in the core +>> driver and are fixed in the first part of this series. +>> +>> The DT frontend is mutually exclusive with ACPI and does not introduce +>> any DT-specific logic into the core. +>> +>> How to test with QEMU +>> -------------------------- +>> Tian Ruidong's QEMU fork [2] emulates AEST MMIO error records on the +>> virt machine.  To test the DT frontend: +>> +>> 1. Build QEMU: +>> +>>       git clone https://github.com/winterddd/qemu.git +>>       cd qemu +>>       git checkout c5e2d5dec9fd62ba622314c40bff0fbecb4dfb34 +>>       ./configure --target-list=aarch64-softmmu +>>       make -j$(nproc) +>> +>> 2. Build the kernel with: +>> +>>       CONFIG_OF_AEST=y +>>       CONFIG_AEST=y +>>       CONFIG_ARM64_RAS_EXTN=y +>>       CONFIG_RAS=y +>> +>> 3. Add the following DT node to your virt machine DTB.  The QEMU +>>     fork maps DRAM error records at 0x090d0000 (SPI 44) and CMN +>>     vendor records at 0x090e0000 (SPI 45): +>> +>>       aest { +>>           compatible = "arm,aest"; +>>           #address-cells = <2>; +>>           #size-cells = <2>; +>>           ranges; +>>           interrupt-parent = <&gic>; +>> +>>           /* DRAM memory node — MMIO at 0x090d0000, SPI 44 */ +>>           aest-dram0@90d0000 { +>>               compatible               = "arm,aest-memory"; +>>               arm,interface-type       = <1>; +>>               arm,group-format         = <0>; +>>               arm,interface-flags      = <0x22>; +>>               arm,num-records          = <4>; +>>               arm,record-impl          = /bits/ 64 <0x0>; +>>               arm,status-report        = /bits/ 64 <0x0>; +>>               arm,addr-mode            = /bits/ 64 <0x0>; +>>               arm,proximity-domain     = <0>; +>>               reg                      = <0x0 0x090d0000 0x0 0x1000>, +>>                                          <0x0 0x090d0800 0x0 0x200>, +>>                                          <0x0 0x090d0e00 0x0 0x100>; +>>               reg-names                = "errblock", "fault-inject", +>>                                          "err-group"; +>>               interrupts               = > IRQ_TYPE_LEVEL_HIGH>; +>>               interrupt-names          = "fhi"; +>>           }; +>>     }; +>> +>> 4. Boot QEMU with acpi=off: +>> +>>       ./qemu-system-aarch64 \ +>>         -machine virt,accel=tcg,gic-version=3 \ +>>         -cpu cortex-a57 -m 2G -smp 4 \ +>>         -kernel Image -dtb virt-aest.dtb \ +>>         -append "console=ttyAMA0 acpi=off earlycon" \ +>>         -nographic +>> +>> 5. Verify probe: +>> +>>       dmesg | grep "DT AEST" +>>       # Expected: DT AEST: registered 1 AEST error source(s) from DT +>>       ls /sys/kernel/debug/aest/ +>> +>> 6. Inject a CE error via the QEMU MMIO fault injection registers. +>>     The QEMU device accepts 64-bit accesses only (use devmem with +>>     the 64-bit width flag): +>> +>>       devmem 0x090d0808 64 0x80000040   # CDOFF | CE inject +>> +>>     This triggers QEMU's error_record_inj_write() which sets +>>     ERRSTATUS.V=1 and asserts the IRQ.  The kernel driver's +>>     aest_irq_func() fires, reads the status, and logs: +>> +>>       AEST: {1}[Hardware Error]: Hardware error from AEST memory.90d0000 +>>       AEST: {1}[Hardware Error]: Error from memory at SRAT proximity +>> domain 0x0 +>> +>> Testing +>> ------- +>> - Validated on Qualcomm's lemans-evk and monaco-evk board with DT boot. +>> - Validated CE and UE injection via debugfs soft_inject. +>> - Tested ACPI path is unaffected: ACPI boot continues to use +>>    drivers/acpi/arm64/aest.c unchanged. +>> +>> [1] https://lore.kernel.org/lkml/20260122094656.73399-1- +>> tianruidong@linux.alibaba.com/ +>> [2] https://github.com/winterddd/qemu/tree/error_record +>> [3] https://developer.arm.com/documentation/den0085/0200/ +>> +>> Signed-off-by: Umang Chheda +>> --- +>> Umang Chheda (8): +>>        ras: aest: Fix shared processor node handling and error log +>> messages +>>        ras: aest: Fix CE/UE error counts not incrementing in debugfs +>>        ras: aest: Skip unimplemented records in debugfs +>>        ras: aest: Add panic_on_ue module parameter +>>        dt-bindings: arm: ras: Introduce bindings for ARM AEST +>>        ras: aest: Add DT frontend for ARM AEST RAS error sources +>>        arm64: dts: qcom: lemans: add AEST error nodes +>>        arm64: dts: qcom: monaco: add AEST error nodes +>> +>>   .../devicetree/bindings/arm/arm,aest.yaml          | 406 +++++++++++++ +>>   arch/arm64/boot/dts/qcom/lemans.dtsi               |  41 ++ +>>   arch/arm64/boot/dts/qcom/monaco.dtsi               |  41 ++ +>>   drivers/ras/aest/Kconfig                           |  15 +- +>>   drivers/ras/aest/Makefile                          |   2 + +>>   drivers/ras/aest/aest-core.c                       |  63 +- +>>   drivers/ras/aest/aest-of.c                         | 673 +++++++++++ +>> ++++++++++ +>>   drivers/ras/aest/aest-sysfs.c                      |  27 +- +>>   drivers/ras/aest/aest.h                            |  15 +- +>>   include/dt-bindings/arm/aest.h                     |  43 ++ +>>   10 files changed, 1310 insertions(+), 16 deletions(-) +>> --- +>> base-commit: a67b7fd0dd1f6ccf3d128dc2099cdb07af1f6a09 +>> change-id: 20260505-aest-devicetree-support-a3722d90e1f5 +>> prerequisite-message-id: <20260122094656.73399-1- +>> tianruidong@linux.alibaba.com> +>> prerequisite-patch-id: c5a7c6431c6c1e6351241e694ee053800039d41d +>> prerequisite-patch-id: 1f6e2c20829eee41a210dd8a538f1e8efcc65872 +>> prerequisite-patch-id: 5556287e3f46c2ed2c0431c53c7782e87bcbd866 +>> prerequisite-patch-id: 2edae0a136d7779b8f686181720e71d044a73311 +>> prerequisite-patch-id: b5190b2844dcb01e72f87a59f3a29548795fdb82 +>> prerequisite-patch-id: 7ba848583708b2ae776a7ce847bb056e3de7f77b +>> prerequisite-patch-id: 397e5b22802b67942435f4f2968f0b1e210ba0e8 +>> prerequisite-patch-id: 2169f4b65537eecbd0ccbd2ad6b28c64ec44655d +>> prerequisite-patch-id: b626f85d98747595b3240bc49e6ad9c9dd5c0fa9 +>> prerequisite-patch-id: 1323dfd2eebad2ef6514dbbce58ba08e8859f894 +>> prerequisite-patch-id: 95b826e5e329408437a3ef336c4f45d4d74f82bb +>> prerequisite-patch-id: b60ff489a5a33c5d5220fa8144af7b7511769cba +>> prerequisite-patch-id: 43f35a52b8a3d13c938ff08083403c1d3bd0df8b +>> prerequisite-patch-id: c55d4e9117ca36d3c2cba82d550a618cb82bb745 +>> prerequisite-patch-id: 3885e10f318ae8101d6909b35d92a976cc359e3c +>> prerequisite-patch-id: 92958cde05577f069c5659018a274bb39cfb6b24 +>> +>> Best regards, +>> -- +>> Umang Chheda +>> +> + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E22368D4C + for ; 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+ Mon, 11 May 2026 23:51:30 -0700 (PDT) +Received: from [10.92.198.185] ([202.46.23.19]) + by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-839683a6252sm22579715b3a.59.2026.05.11.23.51.24 + (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); + Mon, 11 May 2026 23:51:29 -0700 (PDT) +Message-ID: +Date: Tue, 12 May 2026 12:21:22 +0530 +Precedence: bulk +X-Mailing-List: linux-kernel@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +User-Agent: Mozilla Thunderbird +Subject: Re: [PATCH 4/8] ras: aest: Add panic_on_ue module parameter +To: Ruidong Tian , + Ruidong Tian , + Tony Luck + , Borislav Petkov , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Bjorn Andersson , + Konrad Dybcio , catalin.marinas@arm.com, + will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, + mark.rutland@arm.com, Sudeep Holla +Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, + linux-kernel@vger.kernel.org, devicetree@vger.kernel.org +References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> + <20260505-aest-devicetree-support-v1-4-d5d6ffacf0a5@oss.qualcomm.com> + <24e7a997-9479-447e-a1e2-cfab9a904668@linux.alibaba.com> +Content-Language: en-US +From: Umang Chheda +In-Reply-To: <24e7a997-9479-447e-a1e2-cfab9a904668@linux.alibaba.com> +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDA2NSBTYWx0ZWRfX4y/w4nUEnGcF + gW+HVNAV9AIu3PSUNw/wdibLVxrbiPtuHsXzERiVyzCSKV97C0ijtrsyBPio3w4aadbOmj7l7Yg + N+CkkuJj5XrM2P37oDUB56Qw+kgVqieFxFUu3w6HB8DLRKsUn3ZRL/YPDIvsmn6eGJE1KDWCFYf + y4SB+PtQ7qZef2rhuARw9RMfsQrqMkSMsEvQDLmQsUcMPZ9LIL2W4KIMm90Pi2bPzGoieAQlqaA + RTRH96W4jXvHK7mQGvky3WUQjdMVyllBkuKIkO+ngBeV9bN2ua77PgJw/4YH2aL7j2bkbA1qO+F + 6GDGNcDJz/0s22jZ7/hWlJHXvNSN660x1UXAXuypIE5O3XGgkPKM1f0Ye3nbEurbEzYIbTe7Fet + Mtr4mF23fU1CDdzN40IrH57LjAxmTdqq9dyYHIdc8KLfazRnJnOxk9EbU+6xof7kLHM3AaSwEjv + vBmUrdhiUsgZRcCSvqw== +X-Authority-Analysis: v=2.4 cv=Kvp9H2WN c=1 sm=1 tr=0 ts=6a02cdf4 cx=c_pps + a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 + a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 + a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 + a=EUspDBNiAAAA:8 a=XXTmVIMiA0tzt-EScKkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 + a=_Vgx9l1VpLgwpw_dHYaR:22 +X-Proofpoint-ORIG-GUID: Tgi8V-X8ntDsf53gsOGkGTgOByguRUdw +X-Proofpoint-GUID: Tgi8V-X8ntDsf53gsOGkGTgOByguRUdw +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 + definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 + lowpriorityscore=0 impostorscore=0 clxscore=1015 phishscore=0 malwarescore=0 + classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 + reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120065 + +Hi Ruidong, + + +On 5/6/2026 1:36 PM, Ruidong Tian wrote: +> +> +> 在 2026/5/5 20:23, Umang Chheda 写道: +>> The driver unconditionally calls panic() whenever an unrecoverable, +>> uncontainable UE (UET_UC or UET_UEU) is detected. There is no way +>> for the user to suppress this behaviour, which makes it difficult to +>> test UE injection or to run in environments where a kernel panic on +>> every UE is undesirable. +>> +>> Add a module parameter `aest_panic_on_ue` When set to 0 the driver +>> logs the UE and continues instead of panicking. +>> +>> Usage: +>>    # Boot time (kernel cmdline) +>>    aest.aest_panic_on_ue=0 +>> +>>    # Runtime +>>    echo 0 > /sys/module/aest/parameters/aest_panic_on_ue +>> +>> Signed-off-by: Umang Chheda +> +> Hi Umang, +> +> Thanks for the patch. +> +> I understand that this parameter is intended to facilitate UE injection +> testing and to avoid kernel panics in certain environments. However, we +> need to carefully consider the potential risks. +> +> When a UC (Uncontainable Error) or UEU (Unrecoverable Error) occurs, the +> hardware state may be unpredictable, and data integrity cannot be +> guaranteed. Allowing the system to continue running instead of panicking +> in these scenarios could lead to silent data corruption or other +> unforeseen side effects, which poses a significant risk to system +> stability. +> +> For the sake of robustness and data safety, I do not believe we should +> expose an interface that allows users to suppress panic on such critical +> errors. +> +> If the goal is primarily to ease testing, I suggest handling this via +> local driver modifications in your test environment rather than +> upstreaming it as a configurable runtime option. + + +IMO, it would be useful to have a module parameter for this. In some +cases—outside of test scenarios—it’s necessary to avoid triggering a +kernel panic on UE errors. +Would it make sense to keep the default behavior as panic on UE, while +also providing a module parameter to disable it when needed? This way, +we can preserve the default safety behavior while avoiding the need for +local rebuilds just to change this setting. + + +Thanks, +Umang + + +> +> Best regards, +> Ruidong +> +>> --- +>>   drivers/ras/aest/aest-core.c | 9 ++++++++- +>>   1 file changed, 8 insertions(+), 1 deletion(-) +>> +>> diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c +>> index b4f4c975da1d..9ce782a66edf 100644 +>> --- a/drivers/ras/aest/aest-core.c +>> +++ b/drivers/ras/aest/aest-core.c +>> @@ -22,6 +22,11 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); +>>   #undef pr_fmt +>>   #define pr_fmt(fmt) "AEST: " fmt +>>   +static bool aest_panic_on_ue; +>> +module_param(aest_panic_on_ue, bool, 0644); +>> +MODULE_PARM_DESC(aest_panic_on_ue, +>> +         "Panic on unrecoverable error: 0=off 1=on (default: 1)"); +>> + +>>   #ifdef CONFIG_DEBUG_FS +>>   struct dentry *aest_debugfs; +>>   #endif +>> @@ -342,9 +347,11 @@ void aest_proc_record(struct aest_record *record, +>> void *data, bool fake) +>>               aest_record_info( +>>                   record, +>>                   "Simulated error! Skip panic due to fault +>> injection\n"); +>> -        else +>> +        else if (aest_panic_on_ue) +>>               aest_panic(record, ®s, +>>                      "AEST: unrecoverable error encountered"); +>> +        else +>> +            aest_record_err(record, "UE detected, panic suppressed\n"); +>>       } +>>         aest_log(record, ®s); +>> +> + + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 515403B27DB + for ; Tue, 12 May 2026 11:28:51 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 +ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; + t=1778585333; cv=none; b=kltijNPncDp7ImO25FU+OAvda8Hdndjs8gLeVMizJwj9B+RvxmWRenvhI+vaNkoB/ZKFyHvB3T72iXpsBqCTBNgTnCT45W8y7mr4YEwJsD1UlHxHimsHoNzBz4FT+yjCUcSp51ZrYYKn1pZMZQ00qiRHhsM8sS2ri6PDwdsiWDc= +ARC-Message-Signature:i=1; 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[78.88.45.245]) + by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-67ef0b3bb2asm4776531a12.6.2026.05.12.04.28.45 + (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); + Tue, 12 May 2026 04:28:47 -0700 (PDT) +Message-ID: <71eee892-1c0b-49e7-a82d-9016c56e8592@oss.qualcomm.com> +Date: Tue, 12 May 2026 13:28:44 +0200 +Precedence: bulk +X-Mailing-List: linux-kernel@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +User-Agent: Mozilla Thunderbird +Subject: Re: [PATCH 8/8] arm64: dts: qcom: monaco: add AEST error nodes +To: Umang Chheda , + Ruidong Tian , + Tony Luck + , Borislav Petkov , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Bjorn Andersson , + Konrad Dybcio , catalin.marinas@arm.com, + will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, + mark.rutland@arm.com, Sudeep Holla +Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, + linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, + Faruque Ansari +References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> + <20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com> +Content-Language: en-US +From: Konrad Dybcio +In-Reply-To: <20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com> +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 7bit +X-Proofpoint-GUID: wgYegErJV22ILS2NJ0m0EZGUml_L4fHd +X-Proofpoint-ORIG-GUID: wgYegErJV22ILS2NJ0m0EZGUml_L4fHd +X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDExOCBTYWx0ZWRfX5hzuNJvHesXa + JcsS2iUx3MZuPQcpj325OQa/QxB6Ae4S+7KbFTI+irGaoqNJ18pfy5CAxD/hmHbIDf63CoslakR + Zv5kp3bY/IxKuMW2TwiNXifuazIRJ3URc8YTetVZwlWlyRlttDtl7jmRdstyfEbJKDahFCbCGPZ + s9GQeMoAjbsrn4zUvunWL96sg7wulDcvdjloRSE7h/c9Q6m92owlXcHXgtluE0Mf+w63zFdMCRh + hIOiysJ4pw6hdJtmRnd8H1MjupyPJnInhHtvpcQ8SYduOGifSQDLaZk/56gtWNASMA0BxefycSY + LinlCImFQapEi01Lvf8lfZluUlDnD1Tvz2G2PbkZTjyjEjL7mgTa4TwAeOlsHuLNKiQuk7kp3ZV + R9ZIIxVkKvfPTKYZSvMm0HnLl6Wd02oGiQRT0mzRMamM+UU9akAJH0a1O4f2Y3gFNQbeOcnniB/ + lYt1Pa29RaBNaX4u2ew== +X-Authority-Analysis: v=2.4 cv=c6ebhx9l c=1 sm=1 tr=0 ts=6a030ef2 cx=c_pps + a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 + a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 + a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 + a=EUspDBNiAAAA:8 a=LELUAEsiHl5uogXv60kA:9 a=QEXdDO2ut3YA:10 + a=uxP6HrT_eTzRwkO_Te1X:22 +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 + definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 + impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 suspectscore=0 + phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= + route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 + definitions=main-2605120118 + +On 5/5/26 2:23 PM, Umang Chheda wrote: +> Add AEST RAS error source nodes for the Monaco SoC. +> +> The DT describes a processor error source covering all CPU cores and a +> shared L3 cache error source for the cluster. These nodes model the +> hardware error reporting blocks and associated interrupts as required +> by the Arm AEST specification. +> +> Co-developed-by: Faruque Ansari +> Signed-off-by: Faruque Ansari +> Signed-off-by: Umang Chheda +> --- +> arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++++++++++++++++++++++++++++++++++++ +> 1 file changed, 41 insertions(+) +> +> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi +> index 7b1d57460f1e..8e43ceed7d84 100644 +> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi +> @@ -3,6 +3,7 @@ +> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +> */ +> +> +#include +> #include +> #include +> #include +> @@ -29,6 +30,46 @@ / { +> #address-cells = <2>; +> #size-cells = <2>; +> +> + aest { +> + compatible = "arm,aest"; +> + #address-cells = <2>; +> + #size-cells = <2>; +> + ranges; + +These 3 properties aren't necessary if none of the subnodes have a +'reg' property + +Konrad + +From mboxrd@z Thu Jan 1 00:00:00 1970 +Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBB4F43637A; + Wed, 13 May 2026 17:58:26 +0000 (UTC) +Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 +ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; + t=1778695106; cv=none; b=gxJMXTYJuqlPKDErR1olQlVZn/RbwIZQXDq6b2BgcNlNJcBkjztRmhlCGNjXDVZ8i8MVv1o8UeNpcay0GHScpWy3VlOb8xzVbhYUciu9Gws/l0zjPNwZ0TR4HrOF3UJhhtH3LILX9BrUeImnnjNoUk8F5lPT9ow7asNUoj6TVqY= +ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; + s=arc-20240116; t=1778695106; c=relaxed/simple; + bh=AxClpjGMFT/IS8TAonyIRQqd4Y8WS5Q+6hwbcruaAjk=; + h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: + Content-Type:Content-Disposition:In-Reply-To; b=Mp25ko7OMoB/Bvd/RUJp79nNGkPmshPNEpouR8PYe7FB0CyJLIry+ZqAbX3O0V0yHyUcT0uLB1TYGFJKUFJuk0oMMF9as2y580TFrPwzCcBWvY9r4NPHwPif8lBeS3S7yXI2qFCqD35TF3qxEb3ST0o9aySzWV0kABJUTJe8/w0= +ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kpmq3Hq9; arc=none smtp.client-ip=10.30.226.201 +Authentication-Results: smtp.subspace.kernel.org; + dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kpmq3Hq9" +Received: by smtp.kernel.org (Postfix) with ESMTPSA id 05A7FC19425; + Wed, 13 May 2026 17:58:25 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; + s=k20201202; t=1778695106; + bh=AxClpjGMFT/IS8TAonyIRQqd4Y8WS5Q+6hwbcruaAjk=; + h=Date:From:To:Cc:Subject:References:In-Reply-To:From; + b=kpmq3Hq9P0j7QXE+5mLqJHwS1cXfU4Ral57BbyHV3Jd6qqyP9R7+zSbBgS9PTdj2e + ihZOcy9VQYy+u4QJyo10n3O3Oi5JMN7qib0QIkaDNo4QyBo3M2+glGo+sy+KoCQIck + JZDF83e5p8Un0HNHdRuor5wTYoTc0X5+YNv5W2Mf/Vofn1Oc1EprL6u3z1v/ufc1Uw + kJ6G44rhH+pKjSlan3Sn4SpFQ4uDMcZAeuPadtvcdDGR0RxSweyVyOzMaxw4E2YDqj + CKjnHjpdALtpdWZ+pM52fe8BX9O4S0FScN/bfW7UA+7+bqsilwK8ssKJsPTUi1MNN9 + Jg7xPqCjL51kw== +Date: Wed, 13 May 2026 12:58:23 -0500 +From: Rob Herring +To: Umang Chheda +Cc: Ruidong Tian , + Tony Luck , Borislav Petkov , + Krzysztof Kozlowski , + Conor Dooley , + Bjorn Andersson , + Konrad Dybcio , catalin.marinas@arm.com, + will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, + mark.rutland@arm.com, Sudeep Holla , + linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, + linux-kernel@vger.kernel.org, devicetree@vger.kernel.org +Subject: Re: [PATCH 5/8] dt-bindings: arm: ras: Introduce bindings for ARM + AEST +Message-ID: <20260513175823.GA1471517-robh@kernel.org> +References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> + <20260505-aest-devicetree-support-v1-5-d5d6ffacf0a5@oss.qualcomm.com> +Precedence: bulk +X-Mailing-List: linux-kernel@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +Content-Type: text/plain; charset=us-ascii +Content-Disposition: inline +In-Reply-To: <20260505-aest-devicetree-support-v1-5-d5d6ffacf0a5@oss.qualcomm.com> + +On Tue, May 05, 2026 at 05:53:49PM +0530, Umang Chheda wrote: +> The Arm Error Source Table (AEST) specification describes how firmware +> exposes RAS error source topology to the operating system. On ACPI +> systems this information is provided via the AEST ACPI table. +> +> Introduce Device Tree bindings that provide an equivalent description +> of AEST error sources for DT-based platforms. +> +> Signed-off-by: Umang Chheda +> --- +> .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++++++++++ +> include/dt-bindings/arm/aest.h | 43 +++ +> 2 files changed, 449 insertions(+) +> +> diff --git a/Documentation/devicetree/bindings/arm/arm,aest.yaml b/Documentation/devicetree/bindings/arm/arm,aest.yaml +> new file mode 100644 +> index 000000000000..7809a0d38270 +> --- /dev/null +> +++ b/Documentation/devicetree/bindings/arm/arm,aest.yaml +> @@ -0,0 +1,406 @@ +> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +> +%YAML 1.2 +> +--- +> +$id: http://devicetree.org/schemas/arm/arm,aest.yaml# +> +$schema: http://devicetree.org/meta-schemas/core.yaml# +> + +> +title: Arm Error Source Table (AEST) +> + +> +maintainers: +> + - Umang Chheda +> + +> +description: +> + The Arm Error Source Table (AEST) describes RAS error sources and their +> + register interfaces. Each error source exposes one or more error records +> + through either system registers or a memory-mapped register window, and +> + may signal errors via interrupts. The top-level node acts as a container +> + for one or more child nodes, each describing a single AEST error source. +> + Refer to the Arm AEST specification (DEN0085 / DDI 0587B) for details. +> + Flag bit constants for use in DT source files are defined in +> + . +> + +> +properties: +> + compatible: +> + const: arm,aest +> + +> + "#address-cells": +> + const: 2 +> + +> + "#size-cells": +> + const: 2 +> + +> + ranges: true +> + +> +required: +> + - compatible +> + +> +additionalProperties: false +> + +> +patternProperties: +> + "^aest-[a-z0-9-]+(@[0-9a-f]+)?$": +> + type: object +> + description: +> + An AEST error source node describing one error source defined by +> + the Arm AEST specification. +> + +> + properties: +> + compatible: +> + description: +> + Identifies the type of AEST error source. Each value corresponds to +> + a distinct error source class defined by the Arm AEST specification. +> + arm,aest-proxy represents a proxy error source that forwards errors +> + from another error source. +> + enum: +> + - arm,aest-processor +> + - arm,aest-memory +> + - arm,aest-smmu +> + - arm,aest-gic +> + - arm,aest-pcie +> + - arm,aest-vendor +> + - arm,aest-proxy + +This is a fundamental difference how DT and ACPI get structured. ACPI +defines new table for some feature and puts everything in that table. +For DT, these all belong in the node for the corresponding h/w. For +example, if the GIC supports AEST, then that belongs in the GIC node. + +> + +> + reg: +> + description: +> + Register ranges for the error source. Absence of reg implies +> + system-register access (interface type 0). A single range implies +> + memory-mapped access (interface type 1). Two ranges imply +> + single-record memory-mapped access (interface type 2). +> + minItems: 1 +> + maxItems: 4 +> + +> + reg-names: +> + description: +> + Names for the register ranges. The base error-record window is +> + unnamed (or first entry). Optional named ranges provide access to +> + the fault-injection, error-group, and interrupt-config register +> + windows defined by the AEST specification. +> + minItems: 1 +> + maxItems: 4 +> + items: +> + enum: +> + - fault-inject +> + - err-group +> + - irq-config +> + +> + interrupts: +> + description: Interrupts associated with the error source. +> + minItems: 1 +> + maxItems: 2 +> + +> + interrupt-names: +> + description: Names of the interrupts associated with the error source. +> + minItems: 1 +> + maxItems: 2 +> + items: +> + enum: +> + - fhi +> + - eri +> + +> + arm,fhi-flags: +> + description: +> + Bitmask of flags for the fault-handling interrupt (FHI), as defined +> + in the AEST node interrupt structure flags field. Constants are +> + defined in - AEST_IRQ_MODE_LEVEL (0), +> + AEST_IRQ_MODE_EDGE (1). + +DT already has a way to define interrupt flags. Why invent something +new? + +Rob + diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 9ce782a66edfc..8a45727154ec8 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -27,6 +27,117 @@ module_param(aest_panic_on_ue, bool, 0644); MODULE_PARM_DESC(aest_panic_on_ue, "Panic on unrecoverable error: 0=off 1=on (default: 1)"); +static inline void write_errselr_el1(u64 val) +{ + asm volatile("msr s3_0_c5_c3_1, %0" : : "r" (val)); + isb(); +} + +static inline void set_errxctlr_el1(void) +{ + u64 val = 0x10f; + + asm volatile("msr s3_0_c5_c4_1, %0" : : "r" (val)); +} + +static inline void set_errxmisc_overflow(void) +{ + u64 val = 0x7F7F00000000ULL; + + asm volatile("msr s3_0_c5_c5_0, %0" : : "r" (val)); + isb(); +} + +static void initialize_registers(void *info) +{ + set_errxctlr_el1(); + set_errxmisc_overflow(); +} + +static void init_regs_on_cpu(bool all_cpus) +{ + write_errselr_el1(0); + if (all_cpus) + on_each_cpu(initialize_registers, NULL, 1); + else + initialize_registers(NULL); + + write_errselr_el1(1); + initialize_registers(NULL); +} + +#ifdef CONFIG_CPU_PM +static inline u64 read_errxstatus_el1(void) +{ + u64 val; + + asm volatile("mrs %0, s3_0_c5_c4_2" : "=r" (val)); + return val; +} + +static inline void clear_errxstatus_el1(u64 val) +{ + asm volatile("msr s3_0_c5_c4_2, %0" : : "r" (val)); +} + +/* + * Check ERXSTATUS for the currently selected record and clear it if + * V=1. This drains any error that was latched during power collapse + * before we return from the PM notifier — preventing a stale FHI + * interrupt from firing after IRQs are re-enabled and resetting + * ERXMISC0 to 0 via aest_proc_record. + */ +static void aest_check_and_clear_erxstatus(void) +{ + u64 status = read_errxstatus_el1(); + + if (status & ERR_STATUS_V) + clear_errxstatus_el1(status); +} + +static int aest_cpu_pm_notify(struct notifier_block *self, + unsigned long cmd, void *v) +{ + if (cmd != CPU_PM_EXIT && cmd != CPU_PM_ENTER_FAILED) + return NOTIFY_OK; + + /* + * Restore RAS sysregs on this CPU after power collapse, then + * check and clear any pending ERXSTATUS. Matches the downstream + * driver sequence exactly: + * 1. init_regs_on_cpu(false) — restore ERXCTLR + ERXMISC0 + * 2. check record 1 ERXSTATUS (already selected by init_regs_on_cpu) + * 3. check record 0 ERXSTATUS + */ + init_regs_on_cpu(false); + + /* Record 1 is already selected after init_regs_on_cpu(false). */ + aest_check_and_clear_erxstatus(); + + write_errselr_el1(0); + aest_check_and_clear_erxstatus(); + + return NOTIFY_OK; +} + +static struct notifier_block aest_cpu_pm_nb = { + .notifier_call = aest_cpu_pm_notify, +}; + +static void aest_cpu_pm_init(void) +{ + cpu_pm_register_notifier(&aest_cpu_pm_nb); +} + +static void aest_cpu_pm_exit(void) +{ + cpu_pm_unregister_notifier(&aest_cpu_pm_nb); +} +#else +static inline void aest_cpu_pm_init(void) { } +static inline void aest_cpu_pm_exit(void) { } +#endif /* CONFIG_CPU_PM */ + #ifdef CONFIG_DEBUG_FS struct dentry *aest_debugfs; #endif @@ -1020,6 +1131,8 @@ static int aest_device_probe(struct platform_device *pdev) struct aest_device *adev; struct aest_hnode *ahnode; + init_regs_on_cpu(true); + ahnode = *((struct aest_hnode **)pdev->dev.platform_data); if (!ahnode) return -ENODEV; @@ -1067,6 +1180,8 @@ static int aest_device_probe(struct platform_device *pdev) platform_set_drvdata(pdev, adev); + aest_cpu_pm_init(); + aest_dev_init_debugfs(adev); aest_dev_dbg(adev, "Node cnt: %x, id: %x\n", adev->node_cnt, adev->id); @@ -1087,7 +1202,6 @@ static int __init aest_init(void) #ifdef CONFIG_DEBUG_FS aest_debugfs = debugfs_create_dir("aest", NULL); #endif - return platform_driver_register(&aest_driver); } module_init(aest_init);