app: b3rb: add mr_navq95b board

app/b3rb/CMakeLists.txt

@@ -113,9 +113,10 @@ target_sources(app PRIVATE ${SOURCE_FILES})
 
 target_include_directories(app SYSTEM BEFORE PRIVATE ${ZEPHYR_BASE}/include ${CMAKE_BINARY_DIR})
 
-if(CONFIG_BOARD STREQUAL "mr_navq95a")
+if ((CONFIG_BOARD STREQUAL "mr_navq95a") OR
+  (CONFIG_BOARD STREQUAL "mr_navq95b"))
   # Relocate code to ITCM
-  zephyr_linker_sources(ITCM_SECTION boards/mr_navq95a_itcm_linker.ld)
+  zephyr_linker_sources(ITCM_SECTION boards/mr_navq95_itcm_linker.ld)
   zephyr_code_relocate(LIBRARY nanopb LOCATION ITCM_TEXT)
   # Relocate log ring buffer to SDRAM
   zephyr_linker_sources(SECTIONS boards/navq95.ld)

app/b3rb/boards/mr_navq95b_m7_flash.conf

@@ -0,0 +1,116 @@
+CONFIG_ENTROPY_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+CONFIG_SPEED_OPTIMIZATIONS=n
+CONFIG_SIZE_OPTIMIZATIONS=n
+CONFIG_DEBUG_OPTIMIZATIONS=y
+CONFIG_CODE_DATA_RELOCATION=y
+
+CONFIG_DISK_ACCESS=n
+CONFIG_FS_FATFS_EXFAT=n
+CONFIG_DISK_DRIVER_SDMMC=n
+CONFIG_FS_FATFS_MOUNT_MKFS=n
+CONFIG_CEREBRI_SYNAPSE_LOG_SDCARD=y
+CONFIG_RING_BUFFER_LARGE=y
+
+CONFIG_TEST=y
+CONFIG_UBSAN=n
+CONFIG_ASSERT=y
+CONFIG_ASSERT_LEVEL=2
+CONFIG_ASSERT_VERBOSE=y
+
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
+
+CONFIG_STACK_CANARIES=y
+
+CONFIG_ISR_STACK_SIZE=2048
+
+CONFIG_SHELL_STACK_SIZE=4096
+
+CONFIG_LOG_MODE_DEFERRED=y
+CONFIG_LOG_MODE_IMMEDIATE=n
+
+CONFIG_FPU=y
+
+# config
+CONFIG_INPUT=y
+# CONFIG_INPUT_GPIO_KEYS=y (not in dt)
+CONFIG_INPUT_SBUS=y
+CONFIG_INPUT_SBUS_THREAD_STACK_SIZE=1024
+CONFIG_INPUT_SBUS_REPORT_FILTER=0
+CONFIG_INPUT_EVENT_DUMP=n
+CONFIG_INPUT_SHELL=n
+CONFIG_INPUT_MODE_SYNCHRONOUS=y
+
+
+CONFIG_ZROS_SENSE_IMU=y
+#CONFIG_ZROS_SENSE_MAG=y
+CONFIG_CEREBRI_SENSE_SAFETY=n
+
+# I3C tends to lock up the system, needs a driver fix
+CONFIG_ZROS_SENSE_MAG=n
+CONFIG_I3C=n
+CONFIG_BMM350=n
+CONFIG_BMP581=n
+
+CONFIG_CEREBRI_SYNAPSE_ETH_RX=y
+CONFIG_CEREBRI_SYNAPSE_ETH_TX=y
+
+CONFIG_PWM=y
+CONFIG_CEREBRI_ACTUATE_PWM=y
+CONFIG_CEREBRI_ACTUATE_PWM_SHELL=n
+
+CONFIG_LED_STRIP=n
+CONFIG_APA102_STRIP=n
+CONFIG_CEREBRI_ACTUATE_LED_ARRAY=n
+CONFIG_CEREBRI_SENSE_POWER=y
+CONFIG_CEREBRI_ACTUATE_SOUND=n
+
+CONFIG_CAN=y
+CONFIG_CAN_MAX_FILTER=5
+CONFIG_CAN_SHELL=y
+
+CONFIG_NET_DRIVERS=y
+
+CONFIG_NET_SOCKETS_CAN=y
+CONFIG_NET_DEFAULT_IF_CANBUS_RAW=y
+
+CONFIG_CAN_LOG_LEVEL_DBG=n
+CONFIG_CAN_FD_MODE=y
+CONFIG_SHELL_ARGC_MAX=72
+CONFIG_I2C=y
+CONFIG_SENSOR=y
+CONFIG_SENSOR_SHELL=y
+CONFIG_HEAP_MEM_POOL_SIZE=16384
+
+# Debugging
+CONFIG_DEBUG_THREAD_INFO=y
+
+# Logging
+#CONFIG_LOG_BACKEND_NET=n
+#CONFIG_LOG_BACKEND_NET_SERVER="192.0.2.2"
+
+# RPMsg
+CONFIG_IPM=y
+CONFIG_IPM_MBOX=y
+CONFIG_MBOX_NXP_IMX_MU=y
+CONFIG_MBOX_INIT_PRIORITY=0
+CONFIG_OPENAMP=y
+CONFIG_OPENAMP_COPY_RSC_TABLE=y
+CONFIG_OPENAMP_RSC_TABLE_NUM_RPMSG_BUFF=8
+CONFIG_OPENAMP_RSC_TABLE=y
+CONFIG_OPENAMP_MASTER=n
+CONFIG_OPENAMP_WITH_DCACHE=y
+CONFIG_CEREBRI_SYNAPSE_RPMSG=y
+
+# TTY over RPMsg (uncomment block below to enable)
+#CONFIG_SHELL_BACKEND_RPMSG=y
+#CONFIG_SHELL_BACKEND_SERIAL=n
+#CONFIG_ASSERT=n
+
+# Disable fat and enable rpmsgfs
+CONFIG_FILE_SYSTEM_RPMSGFS=y
+CONFIG_FAT_FILESYSTEM_ELM=n
+CONFIG_FILE_SYSTEM_SHELL=y
+
+# Disable atomic 64 support otherwise open-amp cannot be linked
+CONFIG_COMPILER_OPT="-DNO_ATOMIC_64_SUPPORT"

app/b3rb/boards/mr_navq95b_m7_flash.overlay

@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/* Copyright 2025 CogniPilot Foundation */
+#include <freq.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/led/led.h>
+#include <zephyr/dt-bindings/sensor/ina230.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	pwm_actuators: pwm_actuators {
+		compatible = "cerebri,pwm-actuators";
+		aux0 {
+			input-type = "position";
+			input-index = <0>;
+			pwms = <&tpm5 1 PWM_HZ(50) PWM_POLARITY_NORMAL>;
+			disarmed = <1500>;
+			min = <1100>;
+			max = <1900>;
+			center = <1500>;
+			scale = <800>;
+			scale-div = <1>;
+
+		};
+		aux1 {
+			input-type = "velocity";
+			input-index = <0>;
+			pwms = <&tpm3 1 PWM_HZ(20000) PWM_POLARITY_NORMAL>;
+			disarmed = <25000>;
+			min = <0>;
+			max = <50000>;
+			center = <25000>;
+			scale = <717>;
+			scale-div = <1>;
+			use-nano-seconds;
+		};
+		aux2 {
+			input-type = "normalized";
+			input-index = <0>;
+			pwms = <&tpm5 0 PWM_HZ(50) PWM_POLARITY_NORMAL>;
+			disarmed = <0>;
+			min = <0>;
+			max = <20000>;
+			center = <0>;
+			scale = <20000>;
+			scale-div = <1>;
+		};
+	};
+
+	chosen {
+		/* zephyr,canbus = &flexcan5; */
+
+		zephyr,ipc_shm = &shmem;
+		zephyr,ipc_rsc_table = &rsc_table;
+		zephyr,ipc = &mailbox0;
+	};
+
+	ocram: memory@20480000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0x20480000 DT_SIZE_K(256)>;
+		zephyr,memory-region = "OCRAM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+
+	ddr: ddr@90000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0x90000000 DT_SIZE_M(4)>;
+		zephyr,memory-region = "DDR";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+
+	shmem: memory@88000000 {
+		compatible = "mmio-sram";
+		reg = <0x88000000 0x500000>;
+	};
+
+	rsc_table: memory@88220000 {
+		compatible = "mmio-sram";
+		reg = <0x88220000 0x100>;
+	};
+
+	mailbox0: mailbox {
+		compatible = "zephyr,mbox-ipm";
+		mboxes = <&mu7 1>, <&mu7 1>;
+		mbox-names = "tx", "rx";
+		status = "okay";
+	};
+
+	aliases {
+		accel0 = &bmi08x_accel;
+		gyro0 = &bmi08x_gyro;
+		mag0 = &bmm350;
+		power0 = &ina230;
+		wheel-odometry0 = &tpm4;
+		rc = &sbus0;
+		/* can0 = &flexcan5; */
+	};
+};
+
+/* Reconfigure TPM4 as QDEC */
+&tpm4 {
+	compatible = "nxp,tpm-qdec";
+	micro-ticks-per-rev = <685440000>;
+	/delete-property/ prescaler;
+};
+
+&tpm5 {
+	prescaler = <4>;
+};
+
+&lpi2c6 {
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	ina230: ina230@40 {
+		compatible = "ti,ina230";
+		reg = <0x40>;
+		current-lsb-microamps = <10000>;
+		rshunt-micro-ohms = <2000>;
+	};
+};
+
+&lpuart5 {
+	status = "okay";
+	current-speed = <100000>;
+	rx-invert;
+
+	sbus0: sbus {
+		compatible = "futaba,sbus";
+		chan_1 {
+			channel = <1>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <1>;
+		};
+		chan_2 {
+			channel = <2>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <2>;
+		};
+		chan_3 {
+			channel = <3>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <3>;
+		};
+		chan_4 {
+			channel = <4>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <4>;
+		};
+		chan_5 {
+			channel = <5>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <5>;
+		};
+		chan_6 {
+			channel = <6>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <6>;
+		};
+		chan_7 {
+			channel = <7>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <7>;
+		};
+		chan_8 {
+			channel = <8>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <8>;
+		};
+		chan_9 {
+			channel = <9>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <9>;
+		};
+		chan_10 {
+			channel = <10>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <10>;
+		};
+		chan_11 {
+			channel = <11>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <11>;
+		};
+		chan_12 {
+			channel = <12>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <12>;
+		};
+		chan_13 {
+			channel = <13>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <13>;
+		};
+		chan_14 {
+			channel = <14>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <14>;
+		};
+		chan_15 {
+			channel = <15>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <15>;
+		};
+		chan_16 {
+			channel = <16>;
+			type = <INPUT_EV_ABS>;
+			zephyr,code = <16>;
+		};
+	};
+};
+
+&mu7 {
+	status = "okay";
+};

app/rdd2/CMakeLists.txt

@@ -156,7 +156,7 @@ if(CONFIG_BOARD STREQUAL "mr_vmu_tropic")
   zephyr_code_relocate(LIBRARY nanopb LOCATION ITCM_TEXT)
 endif()
 
-if(CONFIG_BOARD STREQUAL "mr_navq95a")
+if(CONFIG_BOARD STREQUAL "mr_navq95a" OR CONFIG_BOARD STREQUAL "mr_navq95b")
   # Relocate code to ITCM
   zephyr_linker_sources(ITCM_SECTION boards/mr_navq95a_itcm_linker.ld)
   zephyr_code_relocate(LIBRARY nanopb LOCATION ITCM_TEXT)