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Core3 updates - #925

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Core3 updates#925
sblantipodi wants to merge 20 commits into
Makuna:CORE3from
sblantipodi:CORE3

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Contained in this PR:

  • Fix(ESP32): add C5 RMT channel handling and improve Core 3 compatibility
  • Add ESP32-C5 RMT channel handling and support channel-aware constructors for the BitBang/CSR-GPIO path.
  • Update related ESP32, ESP8266 and RP2040 include paths and fix ESP32-S2 and ESP-IDF 5.5+ compatibility issues.
  • Improve the ESP32 RMT backend by sizing the RMT buffer according to the target SoC and enabling DMA where available, reducing the risk of transmission underruns caused by WiFi/BLE interrupt preemption.
  • Also remove the obsolete RMT interrupt flag definition used by the legacy IDF v3/v4 driver API.

This PR includes cherry‑picked commits from:

Makuna and others added 20 commits February 21, 2025 14:28
# Conflicts:
#	library.json
#	library.properties
- bit-bang CSR/GPIO
- channel constructor overload
- bit-bang CSR/GPIO
- channel constructor overload
- bit-bang CSR/GPIO
- channel constructor overload
- bit-bang CSR/GPIO
- channel constructor overload
Replace deprecated `gpio_hal_iomux_func_sel()` with `gpio_iomux_out()` for ESP-IDF 5.5+.

- ESP-IDF 5.5.0 removed `gpio_hal_iomux_func_sel()`.
- Use `gpio_iomux_out()` for ESP-IDF 5.5+.
- Maintain backward compatibility with `#ifdef` for older versions.
- Fixes compilation error with pioarduino platform (ESP-IDF 5.5.1).

Tested with:
- pioarduino platform (ESP-IDF 5.5.1, Arduino Core 3.3.4).
- ESP32-S3 boards (Lolin S3 Mini, Seeed XIAO ESP32S3).

Resolves: Makuna#895
config.mem_block_symbols = 192 in NeoEsp32RmtXMethod.h gives the RMT
ping-pong half-buffer only ~96 symbols (~120us at WS2812x 800Kbps).
NimBLE and WiFi event handlers run at higher interrupt priority than
the RMT refill ISR and routinely preempt for longer, leaving the data
line idle past the ~300us LED latch threshold and producing ghost
pixels at 8-pixel intervals.

On chips with DMA-capable RMT (ESP32-S3, ESP32-P4), enable
flags.with_dma and request a generous DMA buffer; DMA decouples the
buffer from RMT channel memory and from ISR refill timing entirely.

On chips without DMA support (ESP32, S2, C3, C6, H2, C5), request the
maximum mem_block_symbols a single TX channel can borrow from its
group (SOC_RMT_TX_CANDIDATES_PER_GROUP * SOC_RMT_MEM_WORDS_PER_CHANNEL),
giving the ISR the most slack each chip can provide.

Also removes NEOPIXELBUS_RMT_INT_FLAGS, a leftover macro from the
legacy IDF v3/v4 driver that is unused by this IDF v5 channel API.

Fixes Makuna#921

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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3 participants