M.Sc Mathematics & Computing · CGPA 8.89/10 (Top 3) · LeetCode Guardian (Global Top 2%, Rating 2000+)
I design and implement production trading infrastructure in modern C++ with measured wire-to-wire latencies under 500ns. Specialized in lock-free concurrency, cache-aware data structures, and kernel-bypass networking for systematic strategies.
Currently: Implementing LSM-tree tick storage with nanosecond-order temporal indexing.
Reading: Inside the Black Box (Rishi K. Narang) · The Linux Programming Interface (Michael Kerrisk)
| System | Latency | Throughput | Architecture | Verification |
|---|---|---|---|---|
| Lock-Free Order Book | <450ns wire-to-wire | 1.2M events/sec | SPSC lock-free queues, cache-line padding, dense price-level arrays, branchless hot-path | rdtsc on Intel Xeon Gold 6248R, perf stat cache-miss profiling, 98% branch prediction accuracy |
| Derivatives Pricer | <12ms per 10M paths | 833K paths/ms | AVX-512 vectorized Monte Carlo, Sobol quasi-random sequences, pybind11 zero-copy bindings | Convergence vs. analytical BS (RMSE < 1e-4), perf SIMD utilization > 92% |
| Market Replay Engine | <2µs replay tick-to-strategy | 50GB+ PCAP ingestion | DPDK kernel-bypass, custom flat-binary serialization, sequential mmap I/O | Deterministic replay: identical strategy outputs across 1000 runs |
| jemalloc Hot-Path | -4% L1/L2 cache misses | — | Concurrent thread-caching arena optimization, false-sharing elimination | perf stat before/after on malloc microbenchmark, merged PR #2967 |
| Model | Method | Convergence | Implementation Detail |
|---|---|---|---|
| Black-Scholes | Closed-form + Greeks | Exact | Analytical delta/gamma/vega/theta/rho, verified against QuantLib |
| Monte Carlo | Quasi-random Sobol, antithetic variates | O(1/N) variance decay | AVX-512 batch path generation, Box-Muller normal transform, early-exercise boundary for American options |
| Stochastic Volatility | Heston model, Milstein scheme | Δt = 1/252, 1M paths | Full truncation scheme for Feller condition, characteristic function pricing for benchmark |
Lock-Free Concurrency
- SPSC/MPSC queues via
std::atomicwith acquire-release semantics - Cache-line padding (
alignas(64)) to eliminate false sharing - Memory ordering:
memory_order_relaxedwhere safe,acquire/releaseon synchronization points
Cache-Aware Design
- Dense arrays for O(1) price-level access (no hash maps on hot path)
- Branch prediction:
__builtin_expecton order-type dispatch, 98%+ accuracy measured - NUMA-aware thread pinning via
sched_setaffinity
Kernel-Bypass Networking
- DPDK poll-mode driver, zero-copy packet processing
- TCP/UDP multicast tuning:
SO_BUSY_POLL,SO_TIMESTAMPING, disabled NAPI - Custom binary serialization: fixed-size structs, no heap allocation on decode
| Repo | Metric | Stack | Topics |
|---|---|---|---|
cpp-lockfree-orderbook |
<450ns wire-to-wire | C++17, Boost.Lockfree, alignas(64) |
high-frequency-trading low-latency cpp17 lock-free matching-engine |
simd-derivatives-pricer |
10M paths <12ms | C++20, AVX-512, pybind11, Python | quantitative-finance monte-carlo simd pybind11 options-pricing |
dpdk-market-replay |
50GB+ PCAP, 300% faster | C++, DPDK, flatbuffers | hft backtesting kernel-bypass pcap market-data |
jemalloc-cache-optimization |
-4% cache misses | C, jemalloc, perf |
memory-allocator performance-engineering cache-optimization open-source |
Competitive Programming
- LeetCode Guardian — Rating 2000+ · Global Top 2% · 500+ problems
- Consistent top 3% in weekly contests under strict time constraints
Open Source
- jemalloc — PR #2967: 4% L1/L2 cache miss reduction in concurrent allocation hot-path
- Methodology:
perf statcache-miss profiling, arena false-sharing elimination
Education
- M.Sc Mathematics and Computing — Stochastic Calculus · Numerical Linear Algebra · Convex Optimization
Target Roles: Quantitative Developer · Low-Latency C++ Engineer · HFT Systems Engineer
Locations: London · Singapore · Hong Kong · Dubai · Remote
Visa: Available for sponsorship (Indian passport)
Email: nitinsaviobada@gmail.com
CV: nitinsaviobada.github.io/resume.pdf