interrupt chip controller drivers

core/arch/arm/kernel/thread.c

@@ -14,6 +14,7 @@
 #include <keep.h>
 #include <kernel/asan.h>
 #include <kernel/boot.h>
+#include <kernel/interrupt.h>
 #include <kernel/linker.h>
 #include <kernel/lockdep.h>
 #include <kernel/misc.h>

core/arch/arm/plat-stm32mp1/plat_tzc400.c

@@ -71,6 +71,7 @@ static bool tzc_region_is_secure(unsigned int i, vaddr_t base, size_t size)
 
 static TEE_Result init_stm32mp1_tzc(void)
 {
+	TEE_Result res = TEE_ERROR_GENERIC;
 	void *base = phys_to_virt(TZC_BASE, MEM_AREA_IO_SEC, 1);
 	unsigned int region_index = 1;
 	const uint64_t dram_start = DDR_BASE;
@@ -108,8 +109,12 @@ static TEE_Result init_stm32mp1_tzc(void)
 			panic("Unexpected TZC area on non-secure region");
 	}
 
-	itr_add(&tzc_itr_handler);
-	itr_enable(tzc_itr_handler.it);
+	res = interrupt_add_handler_with_chip(interrupt_get_main_chip(),
+					      &tzc_itr_handler);
+	if (res)
+		panic();
+
+	interrupt_enable(tzc_itr_handler.chip, tzc_itr_handler.it);
 	tzc_set_action(TZC_ACTION_INT);
 
 	return TEE_SUCCESS;

core/arch/arm/plat-stm32mp1/pm/psci.c

@@ -132,6 +132,8 @@ static void raise_sgi0_as_secure(void)
 
 static void release_secondary_early_hpen(size_t __unused pos)
 {
+	struct itr_chip *itr_chip = interrupt_get_main_chip();
+
 	/* Need to send SIG#0 over Group0 after individual core 1 reset */
 	raise_sgi0_as_secure();
 	udelay(20);
@@ -142,7 +144,7 @@ static void release_secondary_early_hpen(size_t __unused pos)
 		   BOOT_API_A7_CORE1_MAGIC_NUMBER);
 
 	dsb_ishst();
-	itr_raise_sgi(GIC_SEC_SGI_0, TARGET_CPU1_GIC_MASK);
+	itr_chip->ops->raise_sgi(itr_chip, GIC_SEC_SGI_0, TARGET_CPU1_GIC_MASK);
 }
 
 /* Override default psci_cpu_on() with platform specific sequence */

core/arch/arm/plat-synquacer/main.c

@@ -59,8 +59,11 @@ static struct itr_handler timer_itr = {
 
 static TEE_Result init_timer_itr(void)
 {
-	itr_add(&timer_itr);
-	itr_enable(IT_SEC_TIMER);
+	if (interrupt_add_handler_with_chip(interrupt_get_main_chip(),
+					    &timer_itr))
+		panic();
+
+	interrupt_enable(timer_itr.chip, timer_itr.it);
 
 	/* Enable timer FIQ to fetch entropy required during boot */
 	generic_timer_start(TIMER_PERIOD_MS);

core/arch/arm/plat-vexpress/main.c

@@ -101,14 +101,14 @@ static void read_console(void)
 	}
 }
 
-static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused)
+static enum itr_return console_itr_cb(struct itr_handler *hdl)
 {
 	if (notif_async_is_started()) {
 		/*
 		 * Asynchronous notifications are enabled, lets read from
 		 * uart in the bottom half instead.
 		 */
-		itr_disable(IT_CONSOLE_UART);
+		interrupt_disable(hdl->chip, hdl->it);
 		notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF);
 	} else {
 		read_console();
@@ -136,11 +136,11 @@ static void yielding_console_notif(struct notif_driver *ndrv __unused,
 	switch (ev) {
 	case NOTIF_EVENT_DO_BOTTOM_HALF:
 		read_console();
-		itr_enable(IT_CONSOLE_UART);
+		interrupt_enable(console_itr.chip, console_itr.it);
 		break;
 	case NOTIF_EVENT_STOPPED:
 		DMSG("Asynchronous notifications stopped");
-		itr_enable(IT_CONSOLE_UART);
+		interrupt_enable(console_itr.chip, console_itr.it);
 		break;
 	default:
 		EMSG("Unknown event %d", (int)ev);
@@ -154,8 +154,15 @@ struct notif_driver console_notif = {
 
 static TEE_Result init_console_itr(void)
 {
-	itr_add(&console_itr);
-	itr_enable(IT_CONSOLE_UART);
+	TEE_Result res = TEE_ERROR_GENERIC;
+
+	res = interrupt_add_handler_with_chip(interrupt_get_main_chip(),
+					      &console_itr);
+	if (res)
+		return res;
+
+	interrupt_enable(console_itr.chip, console_itr.it);
+
 	if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF))
 		notif_register_driver(&console_notif);
 	return TEE_SUCCESS;

core/drivers/atmel_piobu.c

@@ -13,6 +13,7 @@
 #include <kernel/boot.h>
 #include <kernel/dt.h>
 #include <kernel/dt_driver.h>
+#include <kernel/interrupt.h>
 #include <kernel/pm.h>
 #include <libfdt.h>
 #include <mm/core_memprot.h>
@@ -265,8 +266,16 @@ static struct itr_handler secumod_itr_handler = {
 
 static void secumod_interrupt_init(void)
 {
-	itr_add_type_prio(&secumod_itr_handler, IRQ_TYPE_LEVEL_HIGH, 7);
-	itr_enable(secumod_itr_handler.it);
+	TEE_Result res = TEE_ERROR_GENERIC;
+
+	secumod_itr_handler.chip = interrupt_get_main_chip();
+
+	res = interrupt_add_configure_handler(&secumod_itr_handler,
+					      IRQ_TYPE_LEVEL_HIGH, 7);
+	if (res)
+		panic();
+
+	interrupt_enable(secumod_itr_handler.chip, secumod_itr_handler.it);
 }
 
 static void secumod_cfg_input_pio(uint8_t gpio_pin, uint32_t config)

core/drivers/atmel_saic.c

@@ -29,7 +29,7 @@ struct saic_data {
 	uint32_t external[SAMA5D2_AIC_MAX_IRQS32];
 };
 
-static struct saic_data saic = {0};
+static struct saic_data saic;
 
 static void saic_register_pm(void);
 
@@ -47,7 +47,7 @@ void interrupt_main_handler(void)
 {
 	uint32_t irqnr = saic_read_reg(AT91_AIC_IVR);
 
-	itr_handle(irqnr);
+	interrupt_call_handlers(&saic.chip, irqnr);
 	saic_write_reg(AT91_AIC_EOICR, 0);
 }
 
@@ -149,6 +149,8 @@ static void saic_set_affinity(struct itr_chip *chip __unused,
 
 static const struct itr_ops saic_ops = {
 	.add = saic_add,
+	.mask = saic_disable,
+	.unmask = saic_enable,
 	.enable = saic_enable,
 	.disable = saic_disable,
 	.raise_pi = saic_raise_pi,
@@ -190,9 +192,11 @@ static int saic_dt_get_irq(const uint32_t *properties, int len,
 	return it;
 }
 
-struct itr_chip saic_chip = {
-	.ops = &saic_ops,
-	.dt_get_irq = &saic_dt_get_irq,
+static struct saic_data saic = {
+	.chip = {
+		.ops = &saic_ops,
+		.dt_get_irq = &saic_dt_get_irq,
+	},
 };
 
 static void saic_clear_aicredir(void)
@@ -295,7 +299,7 @@ TEE_Result atmel_saic_setup(void)
 	saic_init_external(fdt, node);
 	saic_init_hw();
 
-	interrupt_main_init(&saic_chip);
+	interrupt_main_init(&saic.chip);
 	saic_register_pm();
 
 	return TEE_SUCCESS;

core/drivers/atmel_wdt.c

@@ -11,8 +11,10 @@
 #include <kernel/delay.h>
 #include <kernel/dt.h>
 #include <kernel/dt_driver.h>
+#include <kernel/interrupt.h>
 #include <kernel/pm.h>
 #include <matrix.h>
+#include <mm/core_mmu.h>
 #include <sama5d2.h>
 #include <tee_api_types.h>
 
@@ -229,7 +231,8 @@ static TEE_Result wdt_node_probe(const void *fdt, int node,
 	uint32_t irq_type = 0;
 	uint32_t irq_prio = 0;
 	int it = DT_INFO_INVALID_INTERRUPT;
-	struct itr_handler *it_hdlr;
+	struct itr_handler *it_hdlr = NULL;
+	TEE_Result res = TEE_ERROR_GENERIC;
 
 	if (fdt_get_status(fdt, node) != DT_STATUS_OK_SEC)
 		return TEE_ERROR_BAD_PARAMETERS;
@@ -240,33 +243,50 @@ static TEE_Result wdt_node_probe(const void *fdt, int node,
 	if (!wdt)
 		return TEE_ERROR_OUT_OF_MEMORY;
 
+	it_hdlr = calloc(1, sizeof(*it_hdlr));
+	if (!it_hdlr) {
+		free(wdt);
+		return TEE_ERROR_OUT_OF_MEMORY;
+	}
+
 	wdt->chip.ops = &atmel_wdt_ops;
 
 	it = dt_get_irq_type_prio(fdt, node, &irq_type, &irq_prio);
 	if (it == DT_INFO_INVALID_INTERRUPT)
-		goto err_free_wdt;
+		goto err_free;
+
+	*it_hdlr = ITR_HANDLER(interrupt_get_main_chip(), it, 0,
+			       atmel_wdt_itr_cb, wdt);
 
-	it_hdlr = itr_alloc_add_type_prio(it, &atmel_wdt_itr_cb, 0, wdt,
-					  irq_type, irq_prio);
-	if (!it_hdlr)
-		goto err_free_wdt;
+	res = interrupt_add_configure_handler(it_hdlr, irq_type, irq_prio);
+	if (res)
+		goto err_free;
 
 	if (dt_map_dev(fdt, node, &wdt->base, &size, DT_MAP_AUTO) < 0)
-		goto err_free_itr_handler;
+		goto err_remove_handler;
 
 	/* Get current state of the watchdog */
 	wdt->mr = io_read32(wdt->base + WDT_MR) & WDT_MR_WDDIS;
 
 	atmel_wdt_init_hw(wdt);
-	itr_enable(it);
+	interrupt_enable(it_hdlr->chip, it_hdlr->it);
+
+	res = watchdog_register(&wdt->chip);
+	if (res)
+		goto err_disable_unmap;
+
 	atmel_wdt_register_pm(wdt);
 
-	return watchdog_register(&wdt->chip);
+	return TEE_SUCCESS;
 
-err_free_itr_handler:
-	itr_free(it_hdlr);
-err_free_wdt:
+err_disable_unmap:
+	interrupt_disable(it_hdlr->chip, it_hdlr->it);
+	core_mmu_remove_mapping(MEM_AREA_IO_SEC, (void *)wdt->base, size);
+err_remove_handler:
+	interrupt_remove_handler(it_hdlr);
+err_free:
 	free(wdt);
+	free(it_hdlr);
 
 	return TEE_ERROR_GENERIC;
 }

core/drivers/crypto/caam/caam_jr.c

@@ -159,7 +159,7 @@ static enum caam_status do_jr_alloc(struct jr_privdata **privdata,
 static enum itr_return caam_jr_irqhandler(struct itr_handler *handler)
 {
 	JR_TRACE("Disable the interrupt");
-	itr_disable(handler->it);
+	interrupt_disable(handler->chip, handler->it);
 
 	/* Send a signal to exit WFE loop */
 	sev();
@@ -582,13 +582,17 @@ enum caam_status caam_jr_init(struct caam_jrcfg *jrcfg)
 	 * Prepare the interrupt handler to secure the interrupt even
 	 * if the interrupt is not used
 	 */
+	jr_privdata->it_handler.chip = interrupt_get_main_chip();
 	jr_privdata->it_handler.it = jrcfg->it_num;
 	jr_privdata->it_handler.flags = ITRF_TRIGGER_LEVEL;
 	jr_privdata->it_handler.handler = caam_jr_irqhandler;
 	jr_privdata->it_handler.data = jr_privdata;
 
 #if defined(CFG_NXP_CAAM_RUNTIME_JR) && defined(CFG_CAAM_ITR)
-	itr_add(&jr_privdata->it_handler);
+	if (interrupt_add_handler(&jr_privdata->it_handler)) {
+		retstatus = CAAM_FAILURE;
+		goto end_init;
+	}
 #endif
 	caam_hal_jr_enable_itr(jr_privdata->baseaddr);
 

core/drivers/gic.c

@@ -11,6 +11,7 @@
 #include <drivers/gic.h>
 #include <keep.h>
 #include <kernel/dt.h>
+#include <kernel/dt_driver.h>
 #include <kernel/interrupt.h>
 #include <kernel/panic.h>
 #include <mm/core_memprot.h>
@@ -94,6 +95,8 @@ static void gic_op_set_affinity(struct itr_chip *chip, size_t it,
 
 static const struct itr_ops gic_ops = {
 	.add = gic_op_add,
+	.mask = gic_op_disable,
+	.unmask = gic_op_enable,
 	.enable = gic_op_enable,
 	.disable = gic_op_disable,
 	.raise_pi = gic_op_raise_pi,
@@ -489,7 +492,7 @@ static void __maybe_unused gic_native_itr_handler(void)
 	id = iar & GICC_IAR_IT_ID_MASK;
 
 	if (id <= gd->max_it)
-		itr_handle(id);
+		interrupt_call_handlers(&gd->chip, id);
 	else
 		DMSG("ignoring interrupt %" PRIu32, id);
 
@@ -585,3 +588,61 @@ static void gic_op_set_affinity(struct itr_chip *chip, size_t it,
 
 	gic_it_set_cpu_mask(gd, it, cpu_mask);
 }
+
+#ifdef CFG_DT
+/* Callback for "interrupt-extended" GIC interrupts in consumer DT nodes */
+static struct itr_desc *dt_get_gic_chip_cb(struct dt_pargs *arg,
+					   void *priv_data, TEE_Result *res)
+{
+	int itr_num = DT_INFO_INVALID_INTERRUPT;
+	struct itr_chip *chip = priv_data;
+	struct itr_desc *desc = NULL;
+	uint32_t type = 0;
+	uint32_t prio = 0;
+
+	itr_num = gic_dt_get_irq(arg->args, arg->args_count, &type, &prio);
+	if (itr_num == DT_INFO_INVALID_INTERRUPT) {
+		*res = TEE_ERROR_GENERIC;
+		return NULL;
+	}
+
+	/* Allocate returned itr_desc as required by dt_get_itr_func type */
+	desc = calloc(1, sizeof(*desc));
+	if (!desc) {
+		*res = TEE_ERROR_OUT_OF_MEMORY;
+		return NULL;
+	}
+
+	gic_op_add(chip, itr_num, type, prio);
+
+	desc->chip = chip;
+	desc->itr_num = itr_num;
+
+	*res = TEE_SUCCESS;
+	return desc;
+}
+
+static TEE_Result gic_probe(const void *fdt, int offs, const void *cd __unused)
+{
+	if (dt_register_interrupt_provider(fdt, offs, dt_get_gic_chip_cb,
+					   &gic_data.chip))
+		panic();
+
+	return TEE_SUCCESS;
+}
+
+static const struct dt_device_match gic_match_table[] = {
+	{ .compatible = "arm,cortex-a15-gic" },
+	{ .compatible = "arm,cortex-a7-gic" },
+	{ .compatible = "arm,cortex-a5-gic" },
+	{ .compatible = "arm,cortex-a9-gic" },
+	{ .compatible = "arm,gic-400" },
+	{ }
+};
+
+DEFINE_DT_DRIVER(gic_dt_driver) = {
+	.name = "gic",
+	.match_table = gic_match_table,
+	.probe = gic_probe,
+};
+#endif /*CFG_DT*/