[BACKPORT] mmcsd: eMMC 4-bit wide bus support for STM32

arch/arm/src/stm32/stm32_sdio.c

@@ -161,6 +161,8 @@
                                   SDIO_CLKCR_WIDBUS_D1)
 #define SDIO_CLKCR_MMCXFR        (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_EDGE | \
                                   SDIO_CLKCR_WIDBUS_D1)
+#define SDIO_CLKCR_MMCXFR4       (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_EDGE | \
+                                  SDIO_CLKCR_WIDBUS_D4)
 #define SDIO_CLCKR_SDXFR         (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \
                                   SDIO_CLKCR_WIDBUS_D1)
 #define SDIO_CLCKR_SDWIDEXFR     (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \
@@ -1764,7 +1766,11 @@ static sdio_statset_t stm32_status(struct sdio_dev_s *dev)
 static void stm32_widebus(struct sdio_dev_s *dev, bool wide)
 {
   struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t widbus = wide ? SDIO_CLKCR_WIDBUS_D4 : SDIO_CLKCR_WIDBUS_D1;
+
   priv->widebus = wide;
+
+  modifyreg32(STM32_SDIO_CLKCR, SDIO_CLKCR_WIDBUS_MASK, widbus);
 }
 
 /****************************************************************************
@@ -1807,6 +1813,12 @@ static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
         clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN);
         break;
 
+      /* Enable in MMC wide (4-bit) operation clocking */
+
+      case CLOCK_MMC_TRANSFER_4BIT:
+        clckr = (SDIO_CLKCR_MMCXFR4 | SDIO_CLKCR_CLKEN);
+        break;
+
       /* SD normal operation clocking (wide 4-bit mode) */
 
       case CLOCK_SD_TRANSFER_4BIT:

arch/arm/src/stm32f7/stm32_sdmmc.c

@@ -202,6 +202,9 @@
 #define STM32_SDMMC_CLKCR_MMCXFR    (STM32_SDMMC_MMCXFR_CLKDIV    | \
                                      STM32_SDMMC_CLKCR_EDGE | \
                                      STM32_SDMMC_CLKCR_WIDBUS_D1)
+#define STM32_SDMMC_CLKCR_MMCXFR4   (STM32_SDMMC_MMCXFR_CLKDIV    | \
+                                     STM32_SDMMC_CLKCR_EDGE | \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D4)
 
 #ifdef STM32_SDMMC_SDXFR_BYPCLKDIV
 #  define STM32_SDMMC_CLCKR_SDXFR     (STM32_SDMMC_CLKCR_BYPASS     | \
@@ -2025,7 +2028,13 @@ static sdio_statset_t stm32_status(struct sdio_dev_s *dev)
 static void stm32_widebus(struct sdio_dev_s *dev, bool wide)
 {
   struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t widbus = wide ? STM32_SDMMC_CLKCR_WIDBUS_D4 :
+                           STM32_SDMMC_CLKCR_WIDBUS_D1;
+
   priv->widebus = wide;
+
+  sdmmc_modifyreg32(priv, STM32_SDMMC_CLKCR_OFFSET,
+                    STM32_SDMMC_CLKCR_WIDBUS_MASK, widbus);
 }
 
 /****************************************************************************
@@ -2069,6 +2078,12 @@ static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
         clckr = (STM32_SDMMC_CLKCR_MMCXFR | STM32_SDMMC_CLKCR_CLKEN);
         break;
 
+      /* Enable in MMC wide (4-bit) operation clocking */
+
+      case CLOCK_MMC_TRANSFER_4BIT:
+        clckr = (STM32_SDMMC_CLKCR_MMCXFR4 | STM32_SDMMC_CLKCR_CLKEN);
+        break;
+
       /* SD normal operation clocking (wide 4-bit mode) */
 
       case CLOCK_SD_TRANSFER_4BIT:

arch/arm/src/stm32h7/stm32_sdmmc.c

@@ -207,6 +207,10 @@
                                      STM32_SDMMC_CLKCR_EDGE       |     \
                                      STM32_SDMMC_CLKCR_PWRSAV     |     \
                                      STM32_SDMMC_CLKCR_WIDBUS_D1)
+#define STM32_SDMMC_CLKCR_MMCXFR4   (STM32_SDMMC_MMCXFR_CLKDIV    |     \
+                                     STM32_SDMMC_CLKCR_EDGE       |     \
+                                     STM32_SDMMC_CLKCR_PWRSAV     |     \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D4)
 #define STM32_SDMMC_CLCKR_SDXFR     (STM32_SDMMC_SDXFR_CLKDIV     |     \
                                      STM32_SDMMC_CLKCR_EDGE       |     \
                                      STM32_SDMMC_CLKCR_PWRSAV     |     \
@@ -2085,7 +2089,24 @@ static sdio_statset_t stm32_status(struct sdio_dev_s *dev)
 static void stm32_widebus(struct sdio_dev_s *dev, bool wide)
 {
   struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t regval;
+
   priv->widebus = wide;
+
+  regval  = sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET);
+  regval &= ~STM32_SDMMC_CLKCR_WIDBUS_MASK;
+
+  if (wide)
+    {
+      regval |= STM32_SDMMC_CLKCR_WIDBUS_D4;
+      regval &= ~STM32_SDMMC_CLKCR_PWRSAV;
+    }
+  else
+    {
+      regval |= STM32_SDMMC_CLKCR_WIDBUS_D1;
+    }
+
+  sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET);
 }
 
 /****************************************************************************
@@ -2129,6 +2150,12 @@ static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
       clckr = STM32_SDMMC_CLKCR_MMCXFR;
       break;
 
+    /* Enable in MMC wide (4-bit) operation clocking */
+
+    case CLOCK_MMC_TRANSFER_4BIT:
+      clckr = STM32_SDMMC_CLKCR_MMCXFR4;
+      break;
+
     /* SD normal operation clocking (wide 4-bit mode) */
 
     case CLOCK_SD_TRANSFER_4BIT:

arch/arm/src/stm32l4/stm32l4_sdmmc.c

@@ -153,6 +153,9 @@
 #define STM32_SDMMC_CLKCR_MMCXFR    (STM32_SDMMC_MMCXFR_CLKDIV    | \
                                      STM32_SDMMC_CLKCR_EDGE | \
                                      STM32_SDMMC_CLKCR_WIDBUS_D1)
+#define STM32_SDMMC_CLKCR_MMCXFR4   (STM32_SDMMC_MMCXFR_CLKDIV    | \
+                                     STM32_SDMMC_CLKCR_EDGE | \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D4)
 #define STM32_SDMMC_CLCKR_SDXFR     (STM32_SDMMC_SDXFR_CLKDIV     | \
                                      STM32_SDMMC_CLKCR_EDGE | \
                                      STM32_SDMMC_CLKCR_WIDBUS_D1)
@@ -1818,7 +1821,13 @@ static sdio_statset_t stm32_status(struct sdio_dev_s *dev)
 static void stm32_widebus(struct sdio_dev_s *dev, bool wide)
 {
   struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t widbus = wide ? STM32_SDMMC_CLKCR_WIDBUS_D4 :
+                           STM32_SDMMC_CLKCR_WIDBUS_D1;
+
   priv->widebus = wide;
+
+  sdmmc_modifyreg32(priv, STM32_SDMMC_CLKCR_OFFSET,
+                    STM32_SDMMC_CLKCR_WIDBUS_MASK, widbus);
 }
 
 /****************************************************************************
@@ -1862,6 +1871,12 @@ static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
         clckr = (STM32_SDMMC_CLKCR_MMCXFR | STM32_SDMMC_CLKCR_CLKEN);
         break;
 
+      /* Enable in MMC wide (4-bit) operation clocking */
+
+      case CLOCK_MMC_TRANSFER_4BIT:
+        clckr = (STM32_SDMMC_CLKCR_MMCXFR4 | STM32_SDMMC_CLKCR_CLKEN);
+        break;
+
       /* SD normal operation clocking (wide 4-bit mode) */
 
       case CLOCK_SD_TRANSFER_4BIT:

arch/risc-v/src/litex/litex_sdio.c

@@ -860,10 +860,12 @@ static int litex_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
 
   /* flush CPU d-cache */
 
+#ifndef CONFIG_LITEX_COHERENT_DMA
   up_invalidate_dcache_all();
+#endif
 
   putreg32(0, LITEX_SDBLOCK2MEM_DMA_ENABLE);
-  putreg32((uintptr_t)buffer >> 32, LITEX_SDBLOCK2MEM_DMA_BASE);
+  putreg32((uintptr_t)(&buffer[4]), LITEX_SDBLOCK2MEM_DMA_BASE);
   putreg32((uintptr_t)buffer, LITEX_SDBLOCK2MEM_DMA_BASE + 0x04);
   putreg32(nbytes, LITEX_SDBLOCK2MEM_DMA_LENGTH);
   putreg32(1, LITEX_SDBLOCK2MEM_DMA_ENABLE);
@@ -903,10 +905,12 @@ static int litex_sendsetup(struct sdio_dev_s *dev,
 
   /* flush CPU d-cache */
 
+#ifndef CONFIG_LITEX_COHERENT_DMA
   up_invalidate_dcache_all();
+#endif
 
   putreg32(0, LITEX_SDMEM2BLOCK_DMA_ENABLE);
-  putreg32((uintptr_t)buffer >> 32, LITEX_SDMEM2BLOCK_DMA_BASE);
+  putreg32((uintptr_t)(&buffer[4]), LITEX_SDMEM2BLOCK_DMA_BASE);
   putreg32((uintptr_t)buffer, LITEX_SDMEM2BLOCK_DMA_BASE + 0x04);
   putreg32(nbytes, LITEX_SDMEM2BLOCK_DMA_LENGTH);
   putreg32(1, LITEX_SDMEM2BLOCK_DMA_ENABLE);

boards/risc-v/litex/arty_a7/Kconfig

@@ -5,6 +5,44 @@
 
 if ARCH_BOARD_ARTY_A7
 
+
+config LITEX_SDIO
+	bool "SDIO"
+	default n
+	select SCHED_HPWORK
+	select MMCSD
+	select MMCSD_SDIO
+	select SDIO_BLOCKSETUP
+	select ARCH_HAVE_SDIO
+	select SDIO_DMA
+
+config LITEX_SDIO1
+	bool "Enable SDIO1"
+	default y if LITEX_SDIO
+	select LITEX_SDIO_DMA
+	depends on LITEX_SDIO
+
+config LITEX_IDMODE_FREQ
+	int "ID mode frequency"
+	default 400000
+	depends on LITEX_SDIO
+	---help---
+		Initial, ID mode SD frequency
+
+config LITEX_MMCXFR_FREQ
+	int "MMC transfer frequency"
+	default 25000000
+	depends on LITEX_SDIO
+	---help---
+		Frequency to use for transferring data to/from an MMC card
+
+config LITEX_SD4BIT_FREQ
+	int "SD 4-bit transfer frequency"
+	default 50000000
+	depends on LITEX_SDIO
+	---help---
+		Frequency to use for transferring data to/from an SD card using all four data lines.
+
 config LITEX_SDIO_MOUNT
 	bool "Mount SDIO at startup"
 	default n

boards/risc-v/litex/arty_a7/configs/sdmmc/defconfig

@@ -0,0 +1,75 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
+# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set
+# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set
+# CONFIG_NSH_DISABLEBG is not set
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="arty_a7"
+CONFIG_ARCH_BOARD_ARTY_A7=y
+CONFIG_ARCH_CHIP="litex"
+CONFIG_ARCH_CHIP_LITEX=y
+CONFIG_ARCH_INTERRUPTSTACK=8192
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BINFMT_DISABLE=y
+CONFIG_BOARD_LOOPSPERMSEC=10000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEFAULT_SMALL=y
+CONFIG_DEV_ZERO=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
+CONFIG_FAT_DMAMEMORY=y
+CONFIG_FAT_FORCE_INDIRECT=y
+CONFIG_FAT_LFN=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FATTIME=y
+CONFIG_FS_PROCFS=y
+CONFIG_GRAN=y
+CONFIG_IDLETHREAD_STACKSIZE=8192
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=8192
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_LITEX_SDIO=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_STRERROR=y
+CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192
+CONFIG_PTHREAD_STACK_DEFAULT=8192
+CONFIG_RAM_SIZE=268435456
+CONFIG_RAM_START=0x40000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=20
+CONFIG_START_MONTH=3
+CONFIG_START_YEAR=2020
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=12
+CONFIG_TESTING_GETPRIME=y
+CONFIG_UART0_RXBUFSIZE=128
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_UART0_TXBUFSIZE=128