Update 2026 03 08 - #27
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NV supports opencl_3d_image_writes according https://developer.nvidia.com/blog/nvidia-is-now-opencl-3-0-conformant/ This PR allows removing explicit enabling of image extensions via -cl-ext command line option, e.g. at https://github.com/intel/llvm/blob/43b3d42e2b2060e9e9e3a96469a1982dc4c10ddd/libclc/CMakeLists.txt#L503
Index 0 is already handled by an early return, so the TODO comment about extracting index 0 from a mask vector is no longer needed.
This aligns us with downstream, where we need to be able to query whether a module depends on CWD or not.
…ed segment load (llvm#184569) The destination vector register group cannot overlap the source vector register group for vector indexed segment load. This patch is to add register overlap checks to the assembler.
Implement RISCV::scanSectionImpl, following the pattern established for x86 (llvm#178846) and AArch64 (llvm#181099). This merges the getRelExpr and TLS handling for SHF_ALLOC sections into the target-specific scanner, enabling devirtualization and eliminating abstraction overhead. - Inline relocation classification into scanSectionImpl with a switch on relocation type, replacing the generic rs.scan() path. - Use processR_PC/processR_PLT_PC for common PC-relative and PLT relocations. - Handle TLS IE and GD directly (RISC-V does not optimize GD/LD/IE). - Replace TLS-optimization-specific expressions for TLSDESC, following the x86 pattern: R_RELAX_TLS_GD_TO_IE -> R_GOT_PC, R_RELAX_TLS_GD_TO_LE -> R_TPREL. Update relocateAlloc and relax() to dispatch on relocation type instead of RelExpr for TLSDESC. - Simplify getRelExpr to only handle relocations needed by relocateNonAlloc and preprocessRelocs. - Remove RISC-V-specific checks from handleTlsRelocation (isRISCV variable, TLSDESC label special cases). - Move R_RISCV_VENDOR handling into the relocation type switch. An undefined vendor symbol now gets the standard undefined symbol error instead of a vendor-specific diagnostic.
…llvm#183861) Whenever an IR use-def edge gets updated, the DAG gets notified about the change by having its `notifySetUse()` callback called. The callback's job is to update the DAG node's `UnscheduledSuccs` counter which is the number of successor nodes that are yet to be scheduled. This update makes sense only if both ends of the use-def edge are in the DAG. Up until now we would still update the counter even if the user was outside the DAG. This patch fixes this, so from now on we skip updatinge `UnscheduledSuccs` if the user is outside the DAG.
…lvm#184693) The previous `_LIBCPP_ASAN_VOLATILE_WRAPPER` approach was used to prevent speculative loads of string data before the short/long state was determined. This patch replaces that mechanism with a more explicit `__annotate_memory_barrier()` using an empty volatile assembly block. This PR is inspired by llvm#183457 and by downstream false positive on `__get_long_size`. It fails same way as `__get_long_pointer` before we have `_LIBCPP_ASAN_VOLATILE_WRAPPER`. Barrier approach avoids expanding `_LIBCPP_ASAN_VOLATILE_WRAPPER` for size_t, and to in general looks more readable. I failed to create reasonable reproducer for test, I suspect it requires precise set of compiler flags, and libc++ site_config which will be hard to maintain in test.
This PR improves MLIR dialect conversion failure diagnostics when legalization fails. Previously, the diagnostic mostly included the operation name (and in partial conversion, whether it was explicitly marked illegal). This change keeps that prefix and appends the printed failing operation. This provides immediate operand/result/type context directly in the same error line. ### Example Before: ``` failed to legalize operation 'test.type_consumer' that was explicitly marked illegal ``` After: ``` failed to legalize operation 'test.type_consumer' that was explicitly marked illegal: "test.type_consumer"(%arg0) : (f32) -> () ``` ### Tests - Updated `mlir/test/Transforms/test-legalizer.mlir` expectations for the richer emitted diagnostic.
…184937) This patch adds custom instruction selection of splat_vector of constants. Rather that using the element size from the VT, find the smallest splat size in the constant. This allow us to use pli.b for i16 or i32 elements that contain a byte splat.
Now that all targets use target-specific relocation scanning for TLS (llvm#181332 RISC-V being the last), handleTlsRelocation is unused.
I have a patch I want to post that improves blend masks, but it ends up with a weird diff in this test stemming from the branch on false. This replaces it with an external boolean. This should still test scalarizing a blend which I believe is the original intent.
…#180473) This is more a user convenience thing. But I thought it helpful. Otherwise, at the moment, the user has to fetch the entire embeddings dict, just to see what all functions a module has
Don't require -memprof-report-hinted-sizes for emitting opt remarks during the thin link step. Invoke the handling also when opt remarks are enabled for MemProf per OptimizationRemarkEmitter::allowExtraAnalysis. Also, add a fallback message if we don't have the context size information, adding tests for those new messages. I also realized we don't currently emit these messages for MemProf with regular LTO, and added a TODO.
) In the Weak Zero SIV tests, given two subscripts `{c0,+,a}` and `c1`, when `c0 == c1`, the tests conclude that a dependency exists from the former subscript at the first iteration to the latter subscript at every iteration. However, this conclusion is correct only when `a` is not zero, which was not being checked. This patch adds non-zero checks for `a` in the Weak Zero SIV tests. Fix the test cases added in llvm#183735 .
…amount. (llvm#184909) If the shift is created during LegalizeVectorOps, the shift amount will be created as a build_vector. Splat_vector is formed by a later DAGCombine. LegalizeVectorOps will visit the new shift before the splat_vector can be created. Handle this case too
For wasm, forming minnum/maxnum style ISD nodes is non-profitable, because (in cases where any float min/max support exists at all), it has pmin/pmax instructions that correspond to the fcmp+select semantics, or relaxed_fmin/relaxed_fmax (for the nnan+nsz case) with even loser semantics. As such, return false from isProfitableToCombineMinNumMaxNum(), and also respect that hook in the SDAGBuilder.
ElementSet and ContainerElementsMap were type aliases inside WaitingOnGraph. This commit replaces the aliases with classes deriving from DenseSet and DenseMap, with convenience operations added for WaitingOnGraph (merge, remove, remove_if, and visit). These convenience functions are used to simplify the implementation of various parts of WaitingOnGraph. Unit tests are added for the convenience operations to improve test coverage. In addition to improving readability of the main WaitingOnGraph operations, this will make it easier to experiment with other underlying representations for these types (e.g. sorted vectors).
`isPeelFirst` and `isPeelLast` are updated only in the Weak Zero SIV tests, and no clients actually use them. Keeping these features while fixing the existing defects in DA would add unnecessary complexity. If they are unnecessary in the first place, it would be better to delete them to mitigate maintenance burden.
…4819) Use the DataLayout-aware TargetFolder instead of ConstantFolder in Clang's CGBuilder. The primary impact of this change is that GEP constant expressions are now emitted in canonical `getelementptr i8` form. This is in preparation for the migration to ptradd, which requires this form. Part of the test updates were performed by Claude Code and reviewed by me.
llvm#184294) This patch fixes generic specialization when the loop dimensions are permuted in the generic w.r.t. to canonical iterator order of the named ops by not forwarding the maps of the original generic and instead recreating them ensuring they always follow the canonical order. For example, the generic which is to be specialized to a matmul could have `[parallel, reduction, parallel]` loops, specializing this as is and just coping the indexing maps like we do now will lead to a verification error since the dimension will not match the canonical form the matmul named op expects e.g. the maps could be: ``` (m, k, n) -> (m,k) ... ``` So we would have to recreate the maps to be: ``` (m,n,k) -> (m,k) ... ``` Assisted by: Claude Code
This PR: Fixes a slight off-by-one error in the check for how many bits are allocated for subreg lane masks. If 65 subreg lanes are used, it fails later, but the error message is not clear as to what has occured.
Minimal infrastructure for a the SymbolLocator plugin that fetches debug info from Microsoft SymStore repositories. More features will follow. SymbolVendorPECOFF was tailored towards DWARF debug info so far. This patch adds code to load the PDB path from the executable and not bail out if DWARF sections are missing, so that in the PDB case we still call `AddSymbolFileRepresentation()` in the very end of `CreateInstance()`. The API test in this patch mocks the directory layout from SymStore, so it doesn't depend on `SymStore.exe` from the Windows SDK. It runs on all platforms that link debug info in a PDB file, which is still just Windows, but it could be cross-platform in principle.
…4782) Fixed small typo. We always send invalidated event, so it is not a real problem.
…84314) This was benign for Linux targets (as when dividing by the scale the offset would be correctly truncated), so only resulted in failures with `-DLLVM_ENABLE_ASSERTIONS=On`. On Windows, this was a miscompile as the lack of alignment would result in the FPR128 callee-save getting assigned to the same offset as the previous GPR. Fixes: llvm#183708
Extract CIR_ComplexPartOp for ComplexRealOp/ComplexImagOp, CIR_ComplexPartPtrOp for ComplexRealPtrOp/ComplexImagPtrOp, CIR_ComplexBinOp for ComplexAddOp/ComplexSubOp, and CIR_ComplexRangeBinOp for ComplexMulOp/ComplexDivOp to eliminate duplicated arguments, results, format, and traits.
… and UF. (llvm#181252)" This reverts commit d7e037c. Recommit with a small fix to properly handle ordered reductions when connecting the epilogue. Original message: Replace manual region dissolution code in simplifyBranchConditionForVFAndUF with using general removeBranchOnConst. simplifyBranchConditionForVFAndUF now just creates a (BranchOnCond true) or updates BranchOnTwoConds. The loop then gets automatically removed by running removeBranchOnConst. This removes a bunch of special logic to handle header phi replacements and CFG updates. With the new code, there's no restriction on what kind of header phi recipes the loop contains. Note that VPEVLBasedIVRecipe needs to be marked as readnone. This is technically unrelated, but I could not find an independent test that would be impacted. The code to deal with epilogue resume values now needs updating, because we may simplify a reduction directly to the start value. PR: llvm#181252
In `simplify()`, we currently skip all columns from 0 to `firstVar` (the column of the pivot) when we eliminate inequalities. This is invalid, because unlike equalities, it is not guaranteed that these columns contain only zeroes, and a scale by `rowMultiplier` cannot be ignored. We must not skip any columns for inequalities.
Need to be careful, when filling the mask for fully matched nodes, the masks may differ in sizes Fixes a crash reported in test/Transforms/SLPVectorizer/X86/mask-size-less-common-mask.ll
… -> PACKSS/US(X,Y) folds. (llvm#178707) If we're just concatenating subvectors together to perform a saturated truncate, see if we can perform PACK on the subvectors directly instead - 256-bit PACK will require a post-shuffle, but this will typically fold away in later shuffle combining and its probably better than changing vector widths with concats. Reference patch based off poor codegen identified in llvm#169995
* Removed an explicit `nb::sig` for `static_typeid`. The inferred type would work just fine, and unqualified `TypeID`, which was there previously, only really works for core types in the `ir` submodule. * `DefaultingPyMlir*` helpers also produce qualified types, e.g. `_mlir.ir.Location` instead of bare `Location`. * `ir.*.__enter__` now returns a concrete type instead of `object`, e.g. `ir.Context.__enter__` returns `Context`. * `loc_tracebacks` uses `Generator` as the return type, since this is what `contextmanager` expects in typeshed. * Changed static methods on subclasses of `DenseElementsAttribute` to return that concrete subclass, instead of `DenseElementsAttribute`. --------- Co-authored-by: Maksim Levental <maksim.levental@gmail.com>
Removes early check, which may prevent some further optimizations, in favor of tree throttling. Reviewers: RKSimon, hiraditya Pull Request: llvm#182760
…part 26) (llvm#185102) Tests converted from test/Lower/Intrinsics: btest.f90, c_associated.f90, c_funloc.f90, cmplx.f90, cpu_time.f90
…#185200) Function types are only allowed to take first-class values as arguments. The LLVM dialect implemented this correctly so far except for allowing opaque struct types. When translated to LLVM proper, invalid IR would be created with confusing assertion errors. This PR matches LLVM by disallowing opaque struct types as arguments, allowing users to catch this kind of mistake early while still in the MLIR world. The corresponding LLVM logic is here: https://github.com/llvm/llvm-project/blob/c4898f3f229027e6cbdf8f9db77b8c14d70f6599/llvm/lib/IR/Type.cpp#L404
…total strided size Added support for zero extending the bitcasted/bswapped type to the original type, if it is larger than the original scalar type Reviewers: hiraditya, RKSimon Pull Request: llvm#184018
This PR introduces the `QualTypeMapper` class, which bridges Clang's type system with the LLVM ABI type system introduced in llvm#158329. The `QualTypeMapper` translates Clang `QualType` instances into their corresponding LLVM ABI type representations, preserving all ABI-relevant information while abstracting away frontend-specific details. The mapper queries the `ASTContext` for layout information computed by the frontend and uses the `TypeBuilder` API(from the above merged PR) to construct the corresponding ABI types. This separation ensures that ABI logic remains independent of frontend AST details while still having access to all necessary type information. This is a prerequisite for implementing target-specific ABI lowering, as demonstrated in llvm#140112
These passes are useful for translating between LLVM proper and the LLVM dialect and have so far been missing in the documentation.
Updates the goto label indentation styles based on the feature request. Resolves llvm#24492.
…0) test (llvm#185289) Inspired by llvm#157687
It looks like llvm#177477 might be caused by OOMs due to running too many link jobs at the same time in rare circumstances. It doesn't reproduce often enough for me to be able to easily check the event logs to confirm the OOM killer was involved (I did try 192 runs), but it doesn't hurt to try. This could slightly decrease performance, but given these are vCPUs, even if we need to run only link jobs, we should take only a 10-20% performance hit for the link phase, which is generally not a large portion of the build.
A miscompilation issue has been addressed via refined handling. Fixes: llvm#114772. Fixes: llvm#63142.
This added a user of the ABI library into clang. We did not have the ABI library set up as a build target yet. This patch does that and also adds the relevant use in clang.
…84966) Adding the missing wwm-regalloc=fast option in 4 more tests that already specify -sgpr-regalloc=fast and -vgpr-regalloc=fast. For consistency, the same preference should be applied to the wwm-regalloc pipeline as well. This is a follow-up to llvm#184190 which addressed the same issue in attr-amdgpu-flat-work-group-size-vgpr-limit.ll.
This change adds direct LLVMIR lowering to the `nvvm.subf` operation added in llvm#179162 to prevent translation failures when canonicalization is not run. Also adds `mlir-translate` tests for `nvvm.subf`. PTX ISA Reference: 1. https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sub 2. https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-sub
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