projects: ad_xband16_ebz: Initial commit

[FilipG24]

PR Description

Add support for AD_XBAND16_EBZ (QUAD-APOLLO) base design for VCU118

This project requires following commits:

• library: Add axi_adf4030 IP for AION bsync and triggers synchronization #2093 (For AION IP support)

For timing closure:

• CPACK/UPACK: Add pipeline support #2092 (Cpack/Upack Pipeline)
• library/jesd204/ad_ip_jesd204_tpl: Add option to bypass pn mon/gen #2095 (Bypass PN_MON/PN_GEN)

HDL doc on this PR: #2033

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[bluncan]

Looks good. Merge it once the other PRs are merged.

[IuliaCMoldovan]

Please make sure you're using the proper license headers for all the files you're adding, and rebase onto latest main, as some of the files you're editing have already the license in place.