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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Windows AMD check of head Setup: Windows 11 Enterprise 22621, WinLibs GCC 15.2 UCRT, Release, Radeon RX 6700 XT 12 GB (discrete RDNA 2), AMD driver 26.10.1. Run with
The Vulkan device was created on both sides, and there were no AI-assisted: yes. |
Thanks for the RX6700 XT check with validation layers; that covers the discrete RDNA 2 case and the VUID check this machine could not run. |
✅ NVIDIA GPU test: passedPR head
Unstable on main (1, these also failed in recent main runs on this machine; not counted against this PR)Failing on main too (3, not counted against this PR)Validation IDs already present on main (9 IDs in 594 tests)Skipped (56)ReproduceAutomated build and test on a contributor's NVIDIA machine; it does not replace upstream CI. A new comment is posted for each new push. Full logs. |
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Windows run on the GPU #15566 was opened on, the integrated Radeon of a Ryzen 7 7700X (1002:164e), with the validation layer that the description's machine didn't have. It fixes the failure there and adds nothing new across the AGC tests.
Head 372b65b5e8 merged onto main ed41d86d32 (clean merge, local only). Windows 11 Home 10.0.26200, WinLibs GCC 16.2.0 (x86_64-ucrt-posix-seh, r3), Release. ANYPS5_REQUIRE_VULKAN=1 ANYPS5_NO_SHADER_CACHE=1 VK_INSTANCE_LAYERS=VK_LAYER_KHRONOS_validation (Vulkan SDK 1.4.363.0; VK_LOADER_DEBUG=layer shows it inserted for the instance and the device), ANYPS5_GPU selecting the device, confirmed by Selected GPU.
| Test | GPU | main |
this PR | this PR with main's SpirvScratchPool.cpp |
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agc_driver_scratch_pool |
Radeon iGPU (1002:164e, subgroup=64), AMD 26.10.2 (32.0.21045.20006) |
0 of 5: scratch pool isolation wave64: round 0 lane 0 dword 0 read 0xdeadbeef, expected 0x00000000 |
5 of 5 | 0 of 5, same message |
RTX 5070 Ti (10de:2c05, subgroup=32), 621.01 |
5 of 5 | 5 of 5 | ||
agc_driver_lds_tree_reduction |
both | 5 of 5 | 5 of 5 |
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Whole AGC set.
ctest -R '^agc' -j 8on each GPU, 1,388 tests:GPU mainthis PR RTX 5070 Ti 1,386 pass 1,386 pass Radeon iGPU 1,385 pass 1,386 pass agc_driver_scratch_poolon the Radeon is the only difference. The other failures, the same on both trees, are tracked:agc_driver_direct_write_completion(#15564) on both GPUs,agc_driver_quad_pixel_mask(#14341) on the RTX, andagc_driver_sample_order_grid_reference(#9503) on the Radeon. -
Validation. No
VUID-line and no missing-layer line in any run, on either tree. -
The scratch tests that don't select a GPU (
agc_flat_scratch,agc_guarded_memory_loads,agc_recorder_upload_scratch,agc_storage_write_back_scratch,agc_spirv_lds_atomic_lock,scalar_scratch_load) pass on the PR.
Non-blocking. check_conventions.py --base main passes, with one warning: the slot-acquisition debt entry is 1,770 characters, over the 1,000-character debt-length limit (957 before). The measurement details could move to this PR's description and the entry keep the gap: the compare-exchange is relaxed and the post-scan barrier acquires at device scope, because AMD's Windows driver turns a storage-buffer acquire into s_barrier; the release store in the divergent exit branch was measured only with this test.
AI-assisted: yes (Claude Code)
The entry grew to 1770 characters with the barrier measurements; the debt-length limit is 1000. The relaxed compare-exchange, the device-scope acquire and the untested release store stay; the driver versions, device ids and timings move to the pull request. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Pushed af84f36: the slot acquisition debt entry is back under the 1000-character limit (992), keeping the gap only; the driver versions, device ids and slot timings moved to the description. No code change. |
Takes main's copy of the eight technical debt files that af84f36 rewrote with CRLF line endings, so the branch changes only SpirvScratchPool.cpp and the slot acquisition debt entry.
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Merged |
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Re-test of the new head, Head merged onto
No AI-assisted: yes (Claude Code) |
What
Fixes #15566.
EmitScratchPoolAcquiretook a scratch pool slot with anOpAtomicCompareExchangewhose semantics wereAcquire | UniformMemoryat device scope, inside the scan that only invocation 0 of the workgroup runs. AMD's Windows driver compiles an acquire on a storage buffer tos_barrier(recorded indocs/dev/debt/shader.mdfor the LDS lock), so on a Radeon 0x13c0 that barrier paired with theOpControlBarrierthe other waves of the workgroup had already reached after the scan: those waves readscratch_pool_slotfrom workgroup memory before invocation 0 stored it, took a garbage slot, and every scratch store and load of theirs went out of the pool (robust access dropped the stores and returned 0). Invocation 0's wave kept the right slot, which is why only lanes 64 and up failed in the test, and why the slot counter never reached 0 and the next dispatch of the program found the lock still held.The compare-exchange is now relaxed, like the atomic load before it, and the
OpControlBarrierafter the scan acquires at device scope instead of workgroup scope, so the ordering the acquire gave moves into uniform flow, where every wave executes the same barrier. The release store of the last invocation keeps its release semantics; it stays in a divergent branch at the end of the program, which the test did not find harmful on that driver. The debt entry on slot acquisition keeps the gap (relaxed compare-exchange, device-scope acquire barrier, release store measured only by this test); the measurements behind it are here: the failure was seen with driver 32.0.21043.5001 on a Radeon1002:13c0and reported with 32.0.21045.20006 on a1002:164e, and the slot scan's cost was measured on an RTX 4090 with about 9 slots of 114696 bytes (APS5_SCRATCH_POOL_MIB=1), where a dispatch of 32768 workgroups takes 1308 ms against 395 ms with the default 64 MiB pool.Overlap:
tools/pr_overlap.pycould not compare #9508, which conflicts withmainand edits the lines aroundOpArrayLengthat the top ofEmitScratchPoolAcquire, next to the constant this change renames; nothing else in code. Whichever merges first, the other rebases.Tested
Windows 11 Pro (10.0.26200), WinLibs GCC 15.2.0 r7 UCRT, Release, on
maina7e817522f(rebased 2026-11-05; themaincolumn was measured onb611e634f7, the change rerun ona7e817522f),ANYPS5_REQUIRE_VULKAN=1 ANYPS5_NO_SHADER_CACHE=1, no validation layer available on this machine.agc_driver_scratch_poolonmain1002:13c0(RDNA 2 integrated, Ryzen, driver 32.0.21043.5001,subgroup=64,mesh 0)scratch pool isolation wave64: round 0 lane 0 dword 0 read 0xdeadbeef, expected 0x00000000subgroup=32)How the cause was found, with the test cut down to the wave64 isolation case on one workgroup: the failure does not depend on the slot count, the delay loop, the program's own
s_barrieror the lane stride, and the pool read back after the dispatch held the stores of lanes 0-63 only, with the lock word still 1 and the counter still 64. Injecting edited SPIR-V into the test: a constant slot 0 instead of the workgroup-memory read passes; an atomic orVolatileworkgroup-memory read still fails; a secondOpControlBarrier, or anOpMemoryBarrierbefore it, passes (that driver compiles both tos_barrier); making the compare-exchange relaxed alone passes 3 of 3, with or without the device-scope barrier.Also run with the change, RTX 4070 unless noted:
agc_driver_lds_tree_reduction(both GPUs),agc_flat_scratchandagc_guarded_memory_loads(both GPUs),agc_recorder_upload_scratch,agc_shader_disk_cache,agc_spirv_branch_targets,agc_spirv_failure_text,agc_spirv_lds_atomic_lock,agc_spirv_module,agc_spirv_narrow_constant_store(all three),agc_spirv_subvector_loop_begin: all pass. Linux, macOS and a title not run; the disk cache rejects entries from another source version, so cached programs are rebuilt.Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed under Silent stubs in their library's technical debt file.mdfiles or images added to the repository (attach them to this PR)🤖 Generated with Claude Code