[morten-holm]

What

s_cselect_b64 sd, exec, 0 (and the same form with vcc or all ones) gives a mask that is the same for every lane. The translation stored it as a plain register pair, so a later read of the pair went through LaneId. Metal has no lane number in a vertex shader, and MoltenVK rejects such a shader ("subgroup capability 61 is unsupported for shader stage 1"), so the draw is skipped.

• s_cselect_b64 with two mask sources now stores the lane bit scc ? source1 : source2 and marks the pair as a mask, the same way v_cmp results are kept. The sources are read before the destination is written.
• A mask of all zero or all one reads as a constant, with no lane number.
• The constant folder folds ((W >> (x & 31)) & 1) != 0 to a constant when W is all zero or all one. Some masks only become constant after folding.

The translation is exact. Nothing changes when the lanes differ.

Tested

• macOS 27 (Apple M2), x86-64 under Rosetta, MoltenVK: one retail title, 30 s run. Before, 8 draws were skipped with "subgroup capability 61 ... stage 1". After, none, and the picture is shown.
• New test agc_constant_bit_test: fails without the fold (all-zero and all-one cases) and passes with it.
• This branch does not build libc on macOS (link.h), so I ran the test and the existing masked-select, control-flow, shader-disk-cache and DPP-write tests on a macOS port tree that carries the same shader code: all pass. The four changed shader files compile on this branch.
• Not tested: Linux and Windows (CI), and the scalarSelectMask64 translation by a unit test; it was only checked end to end on the title above.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source (none added)
• Generic behaviour, not specific to one title
• Depends on: none
• AI-assisted: yes

🤖 Generated with Claude Code

[klosixgaming-arch]

LGTM. Well-structured fix for the s_cselect_b64 mask handling issue on Metal/MoltenVK. The three-part approach is clean: (1) scalarSelectMask64 properly stores lane bits and marks pairs as masks, (2) foldConstantBitTest eliminates LaneId usage for constant all-zero/all-one masks, and (3) threadBit recognizes constant masks upfront. The test specifically validates the folding cases that were failing before. Good end-to-end testing on a retail title showing the MoltenVK error is resolved.

[popcoder565]

Native Windows run, since no Windows results were posted. Setup: Windows 10 (19045), RTX 3060 Laptop (NVIDIA 616.92), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release. Head 8dc1a828, merged onto main 8b393b6 in one build with 31 other PRs that had no Windows run.

• This PR's tests pass: agc_constant_bit_test.
• Full ctest in that build: 520 of 521. The one failure is guest_offline_imports, broken by feat(libSceRudp): implement sceRudpGetStatus #2359 (reported there).

No title was run.

🤖 Addressed by Claude Code

[adriadam10]

Checked: build + ctest on Linux are green, and agc_constant_bit_test fails when the non-test changes are reverted, so the folder part is covered. The translation looks right to me (sources read before the destination is written, same mask-tag pattern as v_cmp).

One thing needed before merging:

• scalarSelectMask64 (ControlFlowInstructions.cpp:247) and the constant paths in readMask/threadBit (ExecMask.cpp:21, :41) are not covered by any test; the PR description says so too. Please add a test (execution, or IR-level next to agc_masked_select_tests) that pins values: scc = 0 and 1, a non-constant source (lanes differ), destination equal to one of the sources, and a wave64 case where the two halves differ.

[morten-holm]

The requested test is in: agc_scalar_select_mask (tests/ScalarSelectMask.cpp, registered next to agc_constant_bit_test). It translates small wave64 vertex programs, runs the IR over every lane and pins the lane values, with scc set and clear, for:

• a source that differs per lane (vcc and exec, in both orders),
• the two wave64 halves differing (vcc holds the lanes below 40),
• a destination that is also a source (s[4:5], and vcc),
• constant sources (exec, zero, -1) and literal sources, including an all-ones literal in wave32 and in wave64.

The constant cases also check that the select keeps both sources as IR constants, which is how threadBit's constant path is covered.

I removed the two constant returns in readMask in the same commit. With them gone the results are identical, because threadBit folds the same constants, so no test can tell them apart and they only added code.

To check that the test can fail, I changed the fix four ways: with s_cselect_b64 reverted it fails (the pair is not marked as a mask), with the two sources swapped it fails on lane values, with the threadBit constant fold disabled it fails on the wave32 case, and without the readMask returns it still passes.

I ran the test on macOS by linking the recompiler objects without libc (main's libc does not build there), so the CI run is its first one through CMake.

@adriadam10 could you take another look?

[adriadam10]

Checked on Linux (build + ctest): agc_constant_bit_test and agc_scalar_select_mask pass, and both fail with the non-test changes reverted. Measured s_cselect_b64 on hardware (gfx1035) with vcc/exec/0/-1/literal/SGPR-pair sources and scc set and clear: the result is scc ? source1 : source2 and a literal is zero-extended, which matches what the tests pin. Thanks for adding the translation test; merging.