[al3w0f205]

What

Expands MaxDispatchVariants from 8 to 32 in DispatchCache.hpp and default variants from 4 to 16 in DispatchCache.cpp.

This prevents compute dispatch variant evictions and pipeline thrashing in titles where compute programs switch across multiple dynamic resource and binding configurations.

All extraneous changes (DMA pattern fill refactoring, reserve optimizations, and group drain modifications) have been dropped to keep this PR strictly focused on the dispatch variant cache.

Tested

• tools/check_conventions.py --base origin/main passes cleanly.
• ctest -R agc_driver passes cleanly.

Checklist

• Depends on: None
• Unblocks: None
• GPUs tested: None
• AI-assisted: yes

[github-actions]

Some comparisons could not be completed because a pull request conflicts with the base branch. Review these shared files manually before concluding that there is no overlap.

Pull request	Shared files not compared
PR 5609	core/libs/prx/libSceAgcDriver/Execution/include/Driver/Dispatch/DispatchCache.hpp
PR 6539	core/libs/prx/libSceAgcDriver/Execution/include/Driver/Dispatch/DispatchCache.hpp
PR 7369	core/libs/prx/libSceAgcDriver/Execution/include/Driver/Dispatch/DispatchCache.hpp
PR 7642	core/libs/prx/libSceAgcDriver/Execution/include/Driver/Dispatch/DispatchCache.hpp
PR 9248	core/libs/prx/libSceAgcDriver/Execution/include/Driver/Dispatch/DispatchCache.hpp
PR 10193	core/libs/prx/libSceAgcDriver/Execution/include/Driver/Dispatch/DispatchCache.hpp

[parl0v]

Data point from a CPU-bound scene on Windows: RTX 3060 12 GB (NVIDIA 617.42), i5-12400F, Windows 10 19045, MinGW GCC Release. Minecraft Dungeons II (PPSA16064 01.100.100), title screen, no input, 200 s rows, APS5_PROFILE_DRAW=1 APS5_PROFILE_GPU=1; main af0fff7 vs main + this PR, interleaved with five other PRs in one batch, two rounds. FPS is the mean of the last 10 [present] windows, GPU busy and idle gaps per frame over the last 8. This scene is CPU-bound on this machine (44-47 ms of idle gaps per frame).

libs	FPS	GPU busy	idle gaps
main	6.61 / 6.76	105 / 104 ms	46 / 44 ms
+ this PR (82119a8)	6.60 / 6.60 (-1.3 %)	105 / 106 ms	47 / 46 ms

Within the run-to-run spread (main itself moved 6.61 -> 6.76 between rounds), no regression, 0 fatal.

AI-assisted: yes (Claude Code)

[nicolasfalesy]

Tested on Linux (Arch), c++ (GCC) 16.2.1 20260810, Release, BUILD_TESTING=ON, main at e3838332ee31af787ad311b7eadbe53d8d012e95. GPU tests ran on lavapipe (llvmpipe, LLVM 22.1.8).

This PR breaks three existing tests: agc_driver_pm4, agc_driver_pipelined_dispatch and agc_driver. On main they pass (2 of 2 full ctest -j8 runs). On main plus this PR each fails (2 of 2):

agc_driver_pm4:               expected PM4 rejection
agc_driver_pipelined_dispatch: a dispatch did not drain the pipeline, and APS5_PIPELINE_DISPATCH is off
agc_driver:                   a copy into host memory drained instead of syncing its source

Each test checks the behaviour this PR changes, so they need to follow it if the change is intended:

1. agc_driver_pm4: the PR replaces require(guarded.empty(), "conditional execution range exceeds its command buffer") (Submission.cpp:159 on main) with code that ends open ranges at the end of the buffer (Submission.cpp:100 and :164 on its head). Pm4.cpp:1067 and :1077 on main still expect the rejection exceeds its command buffer.
2. agc_driver_pipelined_dispatch: Dispatch.cpp:131 on main drains the draw pipeline (Drain(..., 0x15)) before every dispatch. This PR drops that drain and only drains when an HTILE clear overlaps (Dispatch.cpp:139 on its head). PipelinedDispatch.cpp:193 (also :210, :241, :257) requires at least one drain with opcode 0x15 when APS5_PIPELINE_DISPATCH is off. With the old drain put back in front of copyBuffer, the test passes (2 of 2).
3. agc_driver: PacketMemory.cpp:271 turns the pipelined DMA path on by default (APS5_PIPELINE_DMA opt-in on main, APS5_NO_PIPELINE_DMA opt-out here), and :295 drops the 4-byte alignment condition. The PR description does not mention the default change. Submit.cpp:537 counts copiesToHostMemory for a copy into host memory, and that copy now takes the pipelined path instead. With APS5_NO_PIPELINE_DMA=1 agc_driver passes (3 of 3); agc_driver_pm4 and agc_driver_pipelined_dispatch still fail.

AI-assisted: yes

[nicolasfalesy]

Follow-up to my comment above: with this PR, #6914 and #6249 merged together, the pipelined DMA copy path that this PR turns on by default holds back its own source flush. The cause and a tested two-hunk fix are on #6914: #6914 (comment)

AI-assisted: yes

[al3w0f205]

Rebased onto current main and resolved the test regressions:

1. Reverted the Submission.cpp conditional range modification, keeping
   equire(guarded.empty(), "conditional execution range exceeds its command buffer"). �gc_driver_pm4 passes.
2. Restored the pre-dispatch draw pipeline drain when !pipelineCandidate in Dispatch.cpp. �gc_driver_pipelined_dispatch passes.
3. Reverted changing APS5_PIPELINE_DMA to default on in PacketMemory.cpp, keeping it opt-in as on main, and restored the 4-byte alignment check on DMA copy. �gc_driver passes.

Verified locally: �gc_driver, �gc_driver_pm4, and �gc_driver_pipelined_dispatch all pass 100%, and ools/check_conventions.py passes cleanly.

[adriadam10]

Thanks for the rebase and for reverting the parts that broke agc_driver_pm4, agc_driver_pipelined_dispatch and agc_driver. The current head has these problems:

• PacketExecution.cpp:41: the new case 0x50: duplicates the existing case 0x50: { at :45 in the same switch. That is a duplicate case label and does not compile with GCC/MinGW. The existing 0x50 branch already handles the Overlaps check and pipelineDma(); if the overlap check is what you want for pattern fills, change that branch instead.
• PacketExecution.cpp:362-363: the pre-group Drain now only runs with APS5_GROUP_CAPTURE_ALL_QUEUES set. That removes a drain for every group capture on queue 0 by default, which is not described in the PR and no test covers it. Show why it is safe (what the drain protected) and add a test, or drop it.
• PacketMemory.cpp:293: the pattern fill no longer goes through Pm4::ResolveStore, so its size/bounds validation is replaced by fillBytes > immediateLimit only; please keep the Accessible check on the destination and say how this matches the old behaviour for sizes not a multiple of 4.
• Dispatch.cpp:204 is a refactor with no behaviour change, and reserve at :71 likewise; the PR is "one topic", so drop them.
• The PR body (COND_EXEC mapping, Dispatch drain replaced by an overlap check, DMA default on) no longer describes the diff. Please update What/Tested to the real change, and note which of the Overcooked numbers (variant evictions, drains) still hold with only the variants change.

If the Overcooked COND_EXEC crash is still unfixed, that is a separate PR with a test in agc_driver_pm4.

[github-actions]

This pull request is labeled perf, so it needs the summary line of a capture on main and one with the change, from the same title, scene and machine, as the Performance report form asks. Please paste both aps5-summary.jsonl lines, attach the two traces and add the output of tools/trace_digest.py.

[al3w0f205]

Rebased onto current main and scoped this PR strictly to the dispatch variant cache: dropped the DMA pattern fill changes, reserve calls, and group capture drain changes. The PR now cleanly expands MaxDispatchVariants to 32 and default variants from 4 to 16 to eliminate variant thrashing, with conventions and tests passing 100%.

[adriadam10]

Thanks for scoping this down to the variants change. What is missing before it can merge:

• The perf label needs the evidence the bot asked for: the aps5-summary.jsonl line of main and of this PR from the same title, scene and machine, plus the tools/trace_digest.py output. The only measurement in the thread (parl0v, Minecraft Dungeons II, RTX 3060) was taken on the previous head and shows no gain (6.61 → 6.60 FPS); please show a scene where the evictions actually happen and what they cost.
• Memory: this multiplies the compute variants kept per dispatch by 4 (default 4 → 16, cap 8 → 32). State what bounds the total (per dispatch, per shader, per title), what frees the variants, and peak RSS before/after on a workload that hits the bound. NVIDIA pipeline objects are much heavier than RADV/lavapipe, so the default should be measured there; otherwise keep the default and make the larger value opt-in through APS5_DISPATCH_VARIANTS.
• Update What/Tested: ctest -R agc_driver and the conventions check do not show the claimed benefit.

[adriadam10]

Thanks for dropping the default change. What is still missing:

• The PR body is out of date: it says the default goes from 4 to 16 in DispatchCache.cpp, but the head only changes MaxDispatchVariants (8 → 32) in DispatchCache.hpp:24. Please update What/Tested to describe the actual change.
• With the default still 4, nothing changes unless someone sets APS5_DISPATCH_VARIANTS. Show a title/scene where a value above 8 helps: the aps5-summary.jsonl line of main and of this PR (same title, scene, machine, with APS5_DISPATCH_VARIANTS set) plus the tools/trace_digest.py output, as the perf label bot asks. The only measurement in the thread shows no gain.
• Memory: state what bounds the total kept at 32 variants (per dispatch, per shader, per title), what frees them, and peak RSS before/after on a workload that hits the bound. NVIDIA pipeline objects are much heavier than RADV/lavapipe.
• Either that evidence justifies the larger cap, or close this PR.