Hardware design files missing from esp-crab example + scaling to 8-node phase-coherent CSI sounder #259

Checklist

• Checked the issue tracker for similar issues to ensure this is not a duplicate.
• Described the feature in detail and justified the reason for the request.
• Provided specific use cases and examples.

Feature description

Repository: espressif/esp-csi
Path: examples/esp-crab
Related: Issue #18493 (esp-idf)

Summary

The examples/esp-crab directory referenced in ESP-Techpedia as a "Common Crystal Multi-Antenna Solution" for phase-coherent WiFi CSI contains no hardware design files. The schematic, BOM, and PCB layout are needed to implement and scale this design.

Background

I am developing an 8-node phase-coherent WiFi CSI channel sounder using ESP32-C5 for academic MIMO channel sounding research. Phase coherence across all receiver nodes is a hard requirement — independent crystals introduce inter-node CFO that is indistinguishable from channel phase information, making cross-receiver CSI comparison unreliable.

ESP-Techpedia explicitly documents esp-crab as Espressif's solution to this problem:

"We design the common crystal of two chips, which can achieve a similar effect [to multi-antenna research network cards]. esp-crab provides a Wifi-CSI RF phase synchronization solution."

However, examples/esp-crab contains no hardware files.

Request

Please publish or share the following esp-crab hardware design files:

• Schematic (PDF or source)
• BOM
• PCB layout (optional but helpful)

Specific Technical Questions

If the full files cannot be shared, please at minimum clarify:

1. Crystal sharing topology

• Is the crystal shared passively between XTAL_P pins, or through a clock buffer?
• What is the treatment of XTAL_N on slave chip(s) — floating, AC-coupled to GND, or actively driven?
• Are there isolation components (resistors, ferrite beads) on the shared clock line?

2. Oscillator amplifier behavior

• Does the internal Pierce oscillator amplifier on slave chips need to be disabled when driven externally?
• Is there a register or eFuse to put XTAL_P into clock-input mode?
• What are the input voltage swing and impedance requirements for XTAL_P when used as a clock input?

3. Scaling to 8 nodes

• Is a dedicated fanout buffer required for >2 chips?
• Are matched trace lengths between clock outputs required?
• Is there a maximum fanout limit for the shared crystal topology?

4. CSI phase behavior

• With shared clock, are there residual inter-chip phase offsets due to independent PLL lock?
• Does the Wi-Fi stack apply phase corrections or rotations to CSI data before reporting via esp_wifi_set_csi_rx_cb()?
• Is there a hardware timestamp in wifi_csi_info_t tied to the MAC/PHY clock that could be used to align captures across nodes?

Related Issue

GitHub issue espressif/esp-idf#18493 reports that wifi_csi_info_t.buf never changes on ESP32-C5 5 GHz channels. This issue is marked resolved internally — please confirm which ESP-IDF release includes the fix, as the target application uses 5 GHz for sounding.

Environment

Use cases

Distributed 8-node phase-coherent WiFi CSI channel sounder for academic MIMO propagation research. All receiver nodes must share a common frequency reference to maintain phase coherence across CSI measurements. Independent crystals introduce inter-node carrier frequency offset (CFO) that is indistinguishable from channel phase information, making cross-receiver CSI comparison unreliable for AoA estimation and spatial channel characterization.

Alternatives

No response

Additional context

No response