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Network on a Chip (NoC) implementation #5

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@hughperkins

Need a network on a chip implementation

Firstly, what is network on a chip? See https://amstel.estec.esa.int/tecedm/NoC_workshop/GinosarNOC_Tutorial.pdf Buses are becoming spaghetti, so chips nowadays use an internal packet-switching network instead.

Screen Shot 2022-04-07 at 9 05 59 AM

(slide from presentation linked above)

Then the tasks for NoC for VeriGPU are:

  • what implementations currently exist?
  • what do similar projects use?
  • for any existing NoC implementations:
    - good points?
    - anything missing, or not quite working yet?
    - how recently maintained are they? (i.e. are there recent commits?)
    - have they already been used in actual taped-out ASICs?
    - if it looks good, could we get a full independent verification? (you would create this, in a new repo, your own project :) )
    - ideally, including formal verification (again, your own repo, your own project :) )
  • of course, you could provide your own implementation too, but NoC is complex, so simply verifying someone else's NoC is hard. Bear in mind that 80% of semiconductor development in industry is spent on verification.
  • what configuration(s) do you recommend for a GPU? (Please let me know if you need more information on what logical architecture I'm envisaging).
  • Clear documentation on how to integrate the NoC with VeriGPU
  • Ideally, PR that integrates the NoC with VeriGPU (could be multiple PRs)

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