This repository was archived by the owner on Nov 27, 2025. It is now read-only.

Dhawalsr/19.x merge - #108

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dhawalsr wants to merge 38 commits into

intel:npu/release/19.xfrom

dhawalsr:dhawalsr/19.x-merge

Commits on Mar 14, 2025

Fix MLIR-TblGen to fix KW issues (#1)

OrestChura
authored and
rayngun
committed
1847b61
Fix compilation warnings

OrestChura
authored and
rayngun
committed
f9e3ec8
Add flag to disable unused GPU dialects in MLIR

Jackojc
authored and
rayngun
committed
6ec283d
[MLIR] Extend MlirOptMain API to register HW-specific options inside

nikita-kud
authored and
rayngun
committed
f723659
Merge pull request #11 from iszilve/SymbolTableTweaks

nikita-kud
authored and
rayngun
committed
0f31efc
Disable failed tests: #73140

nikita-kud
authored and
rayngun
committed
49d86f2
extend SymbolContainer semantics to SymbolUserMap

istvan.szilveszter@intel.com
authored and
rayngun
committed
060561a
Update PR template

nikita-kud
authored and
rayngun
committed
3613db0
Use virtual inheritance for PassPipelineOptions

nikita-kud
authored and
rayngun
committed
635a6c8

Commits on Mar 18, 2025

Add method getInlineBlockAndPoint for DialectInlinerInterface

nikita-kud
authored and
rayngun
committed
a196b6e

Commits on Mar 19, 2025

PR #38: Replace BaseMemRef/TensorType class with TypeInterface

xin-zhang-intel
authored and
rayngun
committed
dffc016
PR #27: Adding newlines and tracking indent level moved to mlir::AsmPrinter

Jacenty-And-Intel
authored and
rayngun
committed
2c0117d
Added f8E4M3FN and f8E5M2 support to existing QuantizedTypes (17.x) (#37)

AndreiFilipIntel
authored and
rayngun
committed
94f94d4
Customize memref->tensor conversion via dialect interface (#40)

andrey-golubev
authored and
rayngun
committed
106ade6
Initialize pass options using pipeline options

nikita-kud
authored and
rayngun
committed
d0b07d8
Fix compilation issue with MSVC

jschj
authored and
rayngun
committed
dc7e151
SDL security fixes (#32)

authored and
rayngun
committed
d30469f
SDL fixes 2 (#43)

authored and
rayngun
committed
ccde8e0
Port Ubunu-24 warning fixes to npu/release/18.x (#45)

DariaMityagina
authored and
rayngun
committed
133b126
[mlir] Add --list-passes option to mlir-opt (#100420) (#52)

Natan-GabrielTiutiuIntel
authored and
rayngun
committed
4e0fe62
Extend Quant dialect with Quantile Quantization type (#53)

sartil
authored and
rayngun
committed
a1c538d
Bump certifi from 2024.6.2 to 2024.7.4 in /llvm/docs (#48)

dependabot[bot]
authored and
rayngun
committed
5c40209
Bump certifi from 2023.7.22 to 2024.7.4 in /llvm/utils/git (#47)

dependabot[bot]
authored and
rayngun
committed
f1de5a4
Extending QuantileQuantizedType with quantileType mlir::Type member (#60)

sartil
authored and
rayngun
committed
7d1fbfb
[ADT] Require base equality in indexed_accessor_iterator::operator==() (#107856) (#64)

authored and
rayngun
committed
9eafb70
Bump cryptography from 42.0.4 to 43.0.1 in /llvm/utils/git (#59)

dependabot[bot]
authored and
rayngun
committed
2c991dc
Bump cryptography and certifi versions (#65)

Maxim-Doronin
authored and
rayngun
committed
ac485a7
Relax negative scales conditions in Quant Dialect (#61)

ZoranZomborat
authored and
rayngun
committed
7689fc0
Adding missing check in QuantileQuantizedPerAxisType::verify (#66)

sartil
authored and
rayngun
committed
7425f6d
Adding new quantileType types to mlir test (#85)

sartil
authored and
rayngun
committed
47c2393
Revert "Fix MLIR-TblGen to fix KW issues (#1)"
rayngun
committed
f6edb2d
Disable TosaToTensor

ArtemySkrebkov
authored and
rayngun
committed
47ed684
Disable XeGPU

ArtemySkrebkov
authored and
rayngun
committed
a4ee8d0
Linux precommit (#88)

Maxim-Doronin
authored and
rayngun
committed
96b3c90
GitHub Workflow changes
rayngun
committed
ac8630b

Commits on Mar 20, 2025

Fix
rayngun
committed
a74c205

Commits on Mar 21, 2025

EISW-161791 Adding -D macro to avoid compilation failure of mlir-src-sharder
dhawalsr
committed
ea36e32

Commits on Mar 28, 2025

EISW-161791 Setting LLVM_ENABLE_ABI_BREAKING_CHECKS macro to 0 to ensure deterministic hashing
dhawalsr
committed
90e4441