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[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path #10526

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[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path #10526

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1299751
[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path
nanjo712 May 22, 2026
e7c2c5b
fix indentation
nanjo712 May 23, 2026
4367640
use resolveMacroSymName
nanjo712 May 29, 2026
e760eda
fix format
nanjo712 May 29, 2026
f587125
Trigger build
nanjo712 May 29, 2026
97326ff
fix nits
nanjo712 May 30, 2026
92cd9c2
fix format
nanjo712 May 30, 2026
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10 changes: 10 additions & 0 deletions include/circt/Dialect/SV/SVOps.h
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Expand Up @@ -42,6 +42,16 @@ bool isExpression(Operation *op);
/// Returns if the expression is known to be 2-state (binary)
bool is2StateExpression(Value v);

/// Look up or generate the symbol name to use for the `sv.macro.decl`
/// referenced by macro users. Returns the existing decl's sym_name if a
/// `sv.macro.decl` whose Verilog identifier matches `verilogName` already
/// exists in `symbolTableBlock`; otherwise returns a fresh sym_name that does
/// not collide with any existing symbol in `symbolTableBlock`. `created` is set
/// to true iff the returned name belongs to a decl that the caller still needs
/// to materialize.
StringAttr lookupOrGenerateMacroSymName(Block *symbolTableBlock,
StringRef verilogName, bool &created);

//===----------------------------------------------------------------------===//
// CaseOp Support
//===----------------------------------------------------------------------===//
Expand Down
63 changes: 29 additions & 34 deletions lib/Conversion/FIRRTLToHW/LowerToHW.cpp
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Expand Up @@ -2963,43 +2963,38 @@ FIRRTLLowering::lowerSimFormatString(StringRef originalFormatString,
LogicalResult FIRRTLLowering::lowerStatementWithFd(
const FileDescriptorInfo &fileDescriptor, Value clock, Value cond,
const std::function<LogicalResult(Value)> &fn, bool usePrintfCond) {
// Emit an "#ifndef SYNTHESIS" guard into the always block.
bool failed = false;
circuitState.addMacroDecl(builder.getStringAttr("SYNTHESIS"));
addToIfDefBlock("SYNTHESIS", std::function<void()>(), [&]() {
addToAlwaysBlock(clock, [&]() {
// TODO: This is not printf specific anymore. Replace "Printf" with "FD"
// or similar but be aware that changing macro name breaks existing uses.
circuitState.usedPrintf = true;
if (usePrintfCond)
circuitState.addFragment(theModule, "PRINTF_COND_FRAGMENT");

// Emit an "sv.if '`PRINTF_COND_ & cond' into the #ifndef.
Value ifCond = cond;
if (usePrintfCond) {
ifCond =
sv::MacroRefExprOp::create(builder, cond.getType(), "PRINTF_COND_");
ifCond = builder.createOrFold<comb::AndOp>(ifCond, cond, true);
}
addToAlwaysBlock(clock, [&]() {
// TODO: This is not printf specific anymore. Replace "Printf" with "FD"
// or similar but be aware that changing macro name breaks existing uses.
circuitState.usedPrintf = true;
if (usePrintfCond)
circuitState.addFragment(theModule, "PRINTF_COND_FRAGMENT");

Value ifCond = cond;
if (usePrintfCond) {
ifCond =
sv::MacroRefExprOp::create(builder, cond.getType(), "PRINTF_COND_");
ifCond = builder.createOrFold<comb::AndOp>(ifCond, cond, true);
}

addIfProceduralBlock(ifCond, [&]() {
// `fd`represents a file decriptor. Use the stdout or the one opened
// using $fopen.
Value fd;
if (fileDescriptor.isDefaultFd()) {
// Emit the sv.fwrite, writing to stderr by default.
fd = hw::ConstantOp::create(builder, APInt(32, 0x80000002));
} else {
// Call the library function to get the FD.
auto fdOrError = callFileDescriptorLib(fileDescriptor);
if (llvm::failed(fdOrError)) {
failed = true;
return;
}
fd = *fdOrError;
addIfProceduralBlock(ifCond, [&]() {
// `fd`represents a file decriptor. Use the stdout or the one opened
// using $fopen.
Value fd;
if (fileDescriptor.isDefaultFd()) {
// Emit the sv.fwrite, writing to stderr by default.
fd = hw::ConstantOp::create(builder, APInt(32, 0x80000002));
} else {
// Call the library function to get the FD.
auto fdOrError = callFileDescriptorLib(fileDescriptor);
if (llvm::failed(fdOrError)) {
failed = true;
return;
}
failed = llvm::failed(fn(fd));
});
fd = *fdOrError;
}
failed = llvm::failed(fn(fd));
});
});
return failure(failed);
Expand Down
30 changes: 24 additions & 6 deletions lib/Conversion/Utils/SVLoweringUtils.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -62,10 +62,17 @@ void sv::emitFileDescriptorRuntime(Operation *fileScopeOp,
auto getterSymName = ::getFileDescriptorGetterSymName(builder.getContext());
auto fragmentSymName =
::getFileDescriptorFragmentSymName(builder.getContext());
auto macroSymName = builder.getStringAttr(kFileDescriptorMacroName);
auto *fileScopeBlock = &fileScopeOp->getRegion(0).front();
bool fileDescriptorMacroNeedsCreation = false;
auto macroSymName =
sv::lookupOrGenerateMacroSymName(fileScopeBlock, kFileDescriptorMacroName,
fileDescriptorMacroNeedsCreation);
bool synthesisMacroNeedsCreation = false;
auto synthesisSymName = sv::lookupOrGenerateMacroSymName(
fileScopeBlock, "SYNTHESIS", synthesisMacroNeedsCreation);
SymbolTable symbolTable(fileScopeOp);

auto emitGuard = [&](StringRef guard, llvm::function_ref<void(void)> body) {
auto emitGuard = [&](StringAttr guard, llvm::function_ref<void(void)> body) {
sv::IfDefOp::create(
builder, guard, [] {}, body);
};
Expand Down Expand Up @@ -95,15 +102,26 @@ void sv::emitFileDescriptorRuntime(Operation *fileScopeOp,
symbolTable.insert(func);
}

if (!symbolTable.lookup(macroSymName))
symbolTable.insert(sv::MacroDeclOp::create(builder, macroSymName));
if (synthesisMacroNeedsCreation)
symbolTable.insert(sv::MacroDeclOp::create(
builder, builder.getLoc(), synthesisSymName, /*args=*/ArrayAttr{},
/*verilogName=*/synthesisSymName.getValue() == "SYNTHESIS"
? StringAttr{}
: builder.getStringAttr("SYNTHESIS")));

if (fileDescriptorMacroNeedsCreation)
symbolTable.insert(sv::MacroDeclOp::create(
builder, builder.getLoc(), macroSymName, /*args=*/ArrayAttr{},
/*verilogName=*/macroSymName.getValue() == kFileDescriptorMacroName
? StringAttr{}
: builder.getStringAttr(kFileDescriptorMacroName)));

if (symbolTable.lookup(fragmentSymName))
return;

auto fragment = emit::FragmentOp::create(builder, fragmentSymName, [&] {
emitGuard("SYNTHESIS", [&]() {
emitGuard(kFileDescriptorMacroName, [&]() {
emitGuard(synthesisSymName, [&]() {
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@uenoku uenoku Jun 1, 2026

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Can't we remove this?

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@nanjo712 nanjo712 Jun 1, 2026

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I would be more cautious about removing this. We could simply remove the synthesis guard for print operations, mainly because Chisel places these operations in a separate layer, which are then output to separate files. These separate files themselves have macro guard, and also it's easy to disable it by not including these separate files in the synthesis.

As far as I know, there doesn't seem to be a similar mechanism for this part; it outputs separately to each file used, unlike print operations which are separated from the design code.

We might be able to improve it further, but I think this might require another evaluation.

emitGuard(macroSymName, [&]() {
sv::VerbatimOp::create(builder, R"(// CIRCT Logging Library
package __circt_lib_logging;
class FileDescriptor;
Expand Down
25 changes: 25 additions & 0 deletions lib/Dialect/SV/SVOps.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
#include "circt/Dialect/HW/ModuleImplementation.h"
#include "circt/Dialect/SV/SVAttributes.h"
#include "circt/Support/CustomDirectiveImpl.h"
#include "circt/Support/Namespace.h"
#include "circt/Support/ProceduralRegionTrait.h"
#include "mlir/IR/Builders.h"
#include "mlir/IR/BuiltinTypes.h"
Expand Down Expand Up @@ -56,6 +57,30 @@ bool sv::isExpression(Operation *op) {
MacroRefExprOp, MacroRefExprSEOp>(op);
}

StringAttr sv::lookupOrGenerateMacroSymName(Block *symbolTableBlock,
StringRef verilogName,
bool &created) {
for (auto decl : symbolTableBlock->getOps<sv::MacroDeclOp>()) {
if (decl.getMacroIdentifier() == verilogName) {
created = false;
return decl.getSymNameAttr();
}
}

Namespace ns;
auto symbolNameId =
StringAttr::get(symbolTableBlock->getParentOp()->getContext(),
SymbolTable::getSymbolAttrName());
for (auto &op : *symbolTableBlock) {
if (auto symbol = op.getAttrOfType<StringAttr>(symbolNameId))
ns.add(symbol.getValue());
}

created = true;
return StringAttr::get(symbolTableBlock->getParentOp()->getContext(),
ns.newName(verilogName));
}
Comment on lines +70 to +82
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I understand it existed before, but could you consider using SymbolTable::insert instead (as SymbolTable is MLIR proper)?

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@nanjo712 nanjo712 Jun 1, 2026

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I may have misunderstood. I think SymbolTable::insert is not quite appropriate here because this helper simply selects a symbol name and intentionally postpones the creation of the decl opeartion.


/// Returns the operation registered with the given symbol name with the regions
/// of 'symbolTableOp'. recurse through nested regions which don't contain the
/// symboltable trait. Returns nullptr if no valid symbol was found.
Expand Down
27 changes: 2 additions & 25 deletions lib/Dialect/SV/Transforms/SVMaskNonSynthesizable.cpp
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Expand Up @@ -22,7 +22,6 @@
#include "circt/Dialect/SV/SVAttributes.h"
#include "circt/Dialect/SV/SVOps.h"
#include "circt/Dialect/SV/SVPasses.h"
#include "circt/Support/Namespace.h"
#include "circt/Support/ProceduralRegionTrait.h"
#include "circt/Support/Utils.h"
#include "mlir/IR/Builders.h"
Expand Down Expand Up @@ -64,29 +63,6 @@ static Region *getMatchingIfDefElseRegion(Operation *op,
.Default(static_cast<Region *>(nullptr));
}

/// Resolve the symbol name to use for the `sv.macro.decl` referenced by
/// `ifdef` mode's `sv.ifdef` ops. Returns the existing decl's sym_name if a
/// `sv.macro.decl` whose Verilog identifier matches `verilogName` already
/// exists at top level; otherwise returns a fresh sym_name that does not
/// collide with any existing top-level symbol (which may differ from
/// `verilogName` if a non-`sv.macro.decl` symbol of that name is present).
/// `created` is set to true iff the returned name belongs to a decl that
/// the caller still needs to materialize.
static StringAttr resolveMacroSymName(mlir::ModuleOp moduleOp,
StringRef verilogName, bool &created) {
for (auto decl : moduleOp.getOps<sv::MacroDeclOp>()) {
if (decl.getMacroIdentifier() == verilogName) {
created = false;
return decl.getSymNameAttr();
}
}
Namespace ns;
ns.add(moduleOp);
StringRef name = ns.newName(verilogName);
created = true;
return StringAttr::get(moduleOp.getContext(), name);
}

/// `delete` mode: walk the block and erase every masked op.
static void processBlockDelete(Block &block) {
block.walk([&](Operation *op) {
Expand Down Expand Up @@ -164,7 +140,8 @@ void SVMaskNonSynthesizablePass::runOnOperation() {
StringAttr macroSymName;
bool macroDeclNeedsCreation = false;
if (mode == MaskNonSynthesizableMode::Ifdef)
macroSymName = resolveMacroSymName(moduleOp, macro, macroDeclNeedsCreation);
macroSymName = lookupOrGenerateMacroSymName(moduleOp.getBody(), macro,
macroDeclNeedsCreation);

StringRef passDownMacro =
macroSymName ? macroSymName.getValue() : StringRef();
Expand Down
116 changes: 57 additions & 59 deletions test/Conversion/FIRRTLToHW/lower-to-hw.mlir
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Expand Up @@ -362,65 +362,63 @@ firrtl.circuit "Simple" attributes {annotations = [{class =

// CHECK: [[ADDSIGNED:%.+]] = comb.add

// CHECK: sv.ifdef @SYNTHESIS {
// CHECK-NEXT: } else {
// CHECK-NEXT: sv.always posedge [[CLOCK]] {
// CHECK-NEXT: %[[PRINTF_COND:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND]], %reset
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "No operands and literal: %%\0A"
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Binary: %b %0b %4b\0A"([[ADD]], %b, [[ADD]]) : i5, i4, i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Decimal: %d %0d %4d\0A"([[ADD]], %b, [[ADD]]) : i5, i4, i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Hexadecimal: %x %0x %4x\0A"([[ADD]], %b, [[ADD]]) : i5, i4, i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "ASCII Character: %c\0A"([[ADD]]) : i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: [[SUMSIGNED:%.+]] = sv.system "signed"([[ADDSIGNED]])
// CHECK-NEXT: [[DSIGNED:%.+]] = sv.system "signed"(%d)
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Hi signed %d %d\0A"([[SUMSIGNED]], [[DSIGNED]]) : i5, i4
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: sv.fwrite %[[STDERR]], "[%0t]: %d %m"([[TIME]], %a) : i64, i4
// CHECK-NEXT: }
// CHECK-NEXT: sv.if %reset {
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: [[STR:%.+]] = sv.sformatf "%0t%d.txt"([[TIME]], %a) : i64, i4
// CHECK-NEXT: [[FD:%.+]] = sv.func.call.procedural @"__circt_lib_logging::FileDescriptor::get"([[STR]]) : (!hw.string) -> i32
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: sv.fwrite [[FD]], "[%0t]: dynamic file name\0A"([[TIME]]) : i64
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: [[STR:%.+]] = sv.sformatf "%0t%d.txt"([[TIME]], %a) : i64, i4
// CHECK-NEXT: [[FD:%.+]] = sv.func.call.procedural @"__circt_lib_logging::FileDescriptor::get"([[STR]]) : (!hw.string) -> i32
// CHECK-NEXT: sv.fflush fd [[FD]]
// CHECK-NEXT: }
// CHECK: sv.always posedge [[CLOCK]] {
// CHECK-NEXT: %[[PRINTF_COND:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND]], %reset
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "No operands and literal: %%\0A"
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Binary: %b %0b %4b\0A"([[ADD]], %b, [[ADD]]) : i5, i4, i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Decimal: %d %0d %4d\0A"([[ADD]], %b, [[ADD]]) : i5, i4, i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Hexadecimal: %x %0x %4x\0A"([[ADD]], %b, [[ADD]]) : i5, i4, i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: sv.fwrite %[[STDERR]], "ASCII Character: %c\0A"([[ADD]]) : i5
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: [[SUMSIGNED:%.+]] = sv.system "signed"([[ADDSIGNED]])
// CHECK-NEXT: [[DSIGNED:%.+]] = sv.system "signed"(%d)
// CHECK-NEXT: sv.fwrite %[[STDERR]], "Hi signed %d %d\0A"([[SUMSIGNED]], [[DSIGNED]]) : i5, i4
// CHECK-NEXT: }
// CHECK-NEXT: %[[PRINTF_COND_:.+]] = sv.macro.ref.expr @PRINTF_COND_() : () -> i1
// CHECK-NEXT: [[AND:%.+]] = comb.and bin %[[PRINTF_COND_]], %reset : i1
// CHECK-NEXT: sv.if [[AND]] {
// CHECK-NEXT: %[[STDERR:.+]] = hw.constant -2147483646 : i32
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: sv.fwrite %[[STDERR]], "[%0t]: %d %m"([[TIME]], %a) : i64, i4
// CHECK-NEXT: }
// CHECK-NEXT: sv.if %reset {
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: [[STR:%.+]] = sv.sformatf "%0t%d.txt"([[TIME]], %a) : i64, i4
// CHECK-NEXT: [[FD:%.+]] = sv.func.call.procedural @"__circt_lib_logging::FileDescriptor::get"([[STR]]) : (!hw.string) -> i32
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: sv.fwrite [[FD]], "[%0t]: dynamic file name\0A"([[TIME]]) : i64
// CHECK-NEXT: [[TIME:%.+]] = sv.system.time : i64
// CHECK-NEXT: [[STR:%.+]] = sv.sformatf "%0t%d.txt"([[TIME]], %a) : i64, i4
// CHECK-NEXT: [[FD:%.+]] = sv.func.call.procedural @"__circt_lib_logging::FileDescriptor::get"([[STR]]) : (!hw.string) -> i32
// CHECK-NEXT: sv.fflush fd [[FD]]
// CHECK-NEXT: }
firrtl.printf %clock, %reset, "No operands and literal: %%\0A" : !firrtl.clock, !firrtl.uint<1>

%0 = firrtl.add %a, %a : (!firrtl.uint<4>, !firrtl.uint<4>) -> !firrtl.uint<5>
Expand Down
10 changes: 4 additions & 6 deletions test/firtool/lower-layers.fir
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Expand Up @@ -127,12 +127,10 @@ circuit TestHarness:
define trace = x

; CHECK: module TestHarness_Verification()
; CHECK: `ifndef SYNTHESIS
; CHECK: always @(posedge TestHarness.clock) begin
; CHECK: if ((`PRINTF_COND_) & TestHarness.reset)
; CHECK: $fwrite(32'h80000002, "The last PC was: %x", TestHarness.dut.verification.pc_d);
; CHECK: end // always @(posedge)
; CHECK: `endif // not def SYNTHESIS
; CHECK: always @(posedge TestHarness.clock) begin
; CHECK: if ((`PRINTF_COND_) & TestHarness.reset)
; CHECK: $fwrite(32'h80000002, "The last PC was: %x", TestHarness.dut.verification.pc_d);
; CHECK: end // always @(posedge)
; CHECK: endmodule

; CHECK: module TestHarness(
Expand Down
2 changes: 2 additions & 0 deletions unittests/Conversion/CMakeLists.txt
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@@ -1,3 +1,5 @@
add_subdirectory(Utils)

if(CIRCT_SLANG_FRONTEND_ENABLED)
add_subdirectory(ImportVerilog)
endif()
11 changes: 11 additions & 0 deletions unittests/Conversion/Utils/CMakeLists.txt
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@@ -0,0 +1,11 @@
add_circt_unittest(CIRCTConversionUtilsTests
SVLoweringUtilsTest.cpp
)

target_link_libraries(CIRCTConversionUtilsTests
PRIVATE
CIRCTEmit
CIRCTHW
CIRCTSV
CIRCTSVLoweringUtils
)
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