Release Candidate v2.72.0#1423
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Each AXIL transaction previously wrote a single byte to the I2C MUX
channel-select register and assumed the device would atomically replace
the prior channel. On the BittWare XUP-VV8 this leaves enough sticky
state on TCA9548 channels 5 and 7 (QSFP slots 1 and 3) that the second
I2C transaction targeting those slots returns RESP=2 SLVERR and every
subsequent access cascades. Channels 4 and 6 (slots 0, 2) happen to
tolerate the same sequence, which made the failure look QSFP+ specific
when the actual differential is the TCA9548 channel mask.
Insert an explicit deselect-all write (0x00) before the channel-select
write. 0x00 is the documented "no channel selected" state for every
device in I2cMuxPkg.vhd (TCA9548, PCA9547, PCA9544A, PCA9546A, PCA9540B),
so the fix applies uniformly regardless of which decode map is used.
Two new states are added to the existing FSM:
DESELECT_S - waits for the 0x00 write to ack, then loads the saved
target channel mask and pulses i2cRstL low again.
MUX_RST_S - mirrors RST_S but transitions straight to MUX_S so the
deselect path does not re-enter DESELECT_S.
The chanMask record field carries the target channel mask through the
deselect-write phase. Flow is now:
IDLE_S -> RST_S -> DESELECT_S -> MUX_RST_S -> MUX_S -> XBAR_S -> IDLE_S
Validated on a BittWare XUP-VV8 (VU13P) with QSFP28 in slot 0 and QSFP+
modules in slots 1, 2, 3:
Before: slots 1 and 3 fail every transaction after the first one;
Qsfp[1].ReadDevice() cascades into hundreds of SLVERRs.
After: 300/300 ok on every slot in a sustained burst (~940 txn/s),
Qsfp[i].ReadDevice() succeeds on all 4 slots, ErrorCount = 0.
The change is additive for existing surf users - the deselect step is a
single extra I2C byte write per AXIL transaction and gives every
MUX-fronted bus the same clean channel-select handshake regardless of
whether the previous downstream device left the bus in a marginal state.
Removed redundant description attribute causing software to fail
Post-PR #1421 cleanup pass focused on English-word typos in user-facing prose, plus one small kwargs-collision fix retained from the original audit. No behavioural change. Net changes: 143 files, +237/-237 lines. Python typos -- 24 files, 39 fixes Audited every .py under python/ and tests/ via 6 parallel review passes. tests/ was clean. Highlights: analog_devices/_Adt7420.py Analod Deviced -> Analog Devices analog_devices/_Ad9249.py Regsisters -> Registers analog_devices/_Ad9249.py Compliment -> Complement silabs/_Si5{324,326,5345Lite,5394Lite}.py conflagration -> configuration silabs/_Si5345Pages.py Ready Only -> Read Only ti/_Ads54J54.py dcimation -> decimation ti/_Lmk61e2.py retreived -> retrieved xilinx/_AxiSysMonUltraScale.py Managment -> Management xilinx/_AxiSysMonUltraScale.py defatul -> default protocols/jesd204b/_JesdRx.py / _JesdTx.py brake/missaligned/Indicades/undeflow/funtionality/ checkes/re-syncronisations -> fixed British spellings (synchronised, re-synchronisations) preserved where already used. VHDL typos -- 119 files, 197 fixes Audited every .vhd under axi/, base/, devices/, dsp/, ethernet/, protocols/, and xilinx/ via 8 parallel review passes (1146 files total). Only -- comment text was touched. No signal, port, process, entity, generic, or component names were renamed; no string literals in report/assert statements were modified. Most prevalent (boilerplate copy-paste families): 7Series GT clones (gtx7/gth7/gtp7) sucessfully -> successfully (x9) Tranceiver -> Transceiver (x3) PGP Axi banners Errror -> Error (x6) pgp2b/pgp2fc/pgp3 *Pkg / *RxPhy / *RxCell occured -> occurred (x10) XauiCore wrappers adn -> and (x16 in repeated boilerplate) AD9249/AD9681 readout primatives/primative/curDealy -> primitives/primitive/curDelay xvc-udp JTAG paylod/paralle/the the -> fixed Real-English-word substitutions verified per occurrence (not bulk-replaced): weather->whether, it->if, na->and, od->of, got->go, dessert->deassert, rests->resets, with->without, read->ready, an->and, save->same, though->through, knowns->knows, incase->in case, to to->to, the the->the, Interfac e->Interface Pre-flight verified that every misspelled string only appears in -- comment lines (never as an identifier or in code) before any bulk substitution. British spellings preserved. AdcTester kwargs fix -- 1 file The only kwarg-hardening change retained from the post-PR #1421 audit: python/surf/devices/analog_devices/_Ad9249.py AdcTester.__init__ accepts description as a named parameter, eliminating the TypeError: got multiple values for keyword argument 'description' when a caller passes description=. The other 8 wrappers identified in the original audit (AxiMonAxiL, Ltm4664, Si5345, Si5394, PhantomS711, PMBus, Pgp3AxiL, Pgp4AxiL) were prepared but reverted; they remain at their pre-release shape. Verification: python -m compileall -f python/ -- clean flake8 --count python/ -- 0 scripts/vsg_linter.sh -- No issues found cocotb regression suite NOT run locally; it requires the make MODULES=$PWD import HDL pipeline only available in CI.
Typo cleanup: Python descriptions/comments and VHDL comments
AxiLiteCrossbarI2cMux: deselect TCA9548 channels between transactions
Add targeted cocotb regression coverage for FIFO pressure and recovery, RAM collision and enable semantics, SynchronizerFifo read-enable gaps, Arbiter starvation rotation, WatchDogRst near-timeout keepalive noise, and SlvDelayFifo/SlvDelayRam reset and runtime-delay behavior. Document the SlvDelayRam runtime maxCount contract in the RTL description header. Formalize the cocotb regression test style guide in tests/README.md and refine the CoaXPress regression docs and tests.
Deepen base regression coverage
Document SURF agent and contributor conventions
When a continued (multi-buffer) frame fills a buffer exactly on an AXI
burst boundary, AxiStreamDmaV2Write falls through MOVE_S -> IDLE_S ->
ADDR_S and issues one more burst at the next buffer's base address before
the MOVE_S overflow check triggers the continue. With maxSize already
zero this is a degenerate zero-length burst at the buffer boundary:
* Simulation: getAxiLen() is called with length 0 (typed
"integer range 1 to 4096") -> bound-check failure.
* Hardware: the off-by-one address is one element past the buffer.
For the on-chip HBM store-and-forward (HbmDmaBuffer/HbmDmaBufferV2,
which wrap AxiStreamDmaV2Fifo) it lands in the next contiguous buffer
and is masked, corrupting frames larger than the per-buffer frame size
(512 KiB on the XilinxVariumC1100). For the host PCIe DMA, where each
continued buffer is a separately-mapped page, it lands past the
mapping and raises an IOMMU IO_PAGE_FAULT once frames exceed the host
buffer size (2 MiB).
Detect the exact-fill-on-burst-boundary case at burst completion and
start the continue there (return the descriptor with continue set,
release the buffer) instead of re-entering ADDR_S, so no boundary burst
is emitted. contEn=0 keeps the legacy overflow/drop path unchanged.
Add two cocotb regression benches:
* test_AxiStreamDmaV2FifoLoopback.py -- streams a frame through
AxiStreamDmaV2Fifo (AxiRam-backed M_AXI) and checks it is re-merged
byte-for-byte; frames crossing the buffer boundary failed before.
* test_AxiStreamDmaV2WriteContinue.py -- drives a multi-buffer continue
with distinct, gapped buffer addresses and asserts every write burst
stays inside a declared buffer window (the IOMMU-fault signature).
Full tests/axi/dma suite passes (21 tests).
…ener) rogue is removing addPreWriteListener()/pr.WriteBlockedError (PR #1248 reverts PR #1229), which the CoaXPress write guard depended on. Reimplement the guard locally so the drivers work on both current and future rogue. - Add _WriteGuard.py: local WriteBlockedError plus WriteGuardMixin, which restores the addPreWriteListener API by overriding Device.writeBlocks (the funnel for interactive RemoteVariable.set writes). - Bootstrap, PhantomS641, PhantomS991 inherit the mixin; the _write_guard bodies and addPreWriteListener calls are unchanged. PhantomS711 inherits via PhantomS641. - Drop rogue.Version.minVersion('6.13.0') and the now-unused import rogue. Behavior matches addPreWriteListener + rogue v6.13.0: only single interactive writes are guarded; bulk writeAll/setYaml and posted acquisition commands pass.
…ss widths - Replace dmaAck.size(RAM_DATA_WIDTH_C-1 downto 0) with resize(): the slice indexed past the fixed 32-bit size field whenever ADDR_WIDTH_C > 32, failing Vivado elaboration (Synth 8-97 array index out of range). - Keep the endRamSize remaining-bytes math in the vector domain: conv_integer asserts in simulation when the 33-bit-plus difference exceeds integer'high.
- Add AXI_ADDR_WIDTH_G generic to AxiStreamDmaRingWrite/Read IpIntegrators (default 16 preserves existing behavior) and wire it through AXI_CONFIG_C, MasterAxiIpIntegrator, and the M_AXI address port widths. - Sweep both cocotb tests with a wide_addr_33bit case so GHDL elaborates the ADDR_WIDTH_C > 32 configuration that previously only Vivado builds reached. Generic-dependent bound errors on the wide-address path now fail CI.
Add CODEOWNERS review requirement
Reimplement CoaXPress write guard locally (drop rogue addPreWriteListener)
…-release Fix AxiStreamDmaRingWrite elaboration for >32-bit AXI address widths
axi: fix AxiStreamDmaV2 stray write burst at continued buffer boundary
Thin flattened-port wrappers under protocols/packetizer/wrappers/ so cocotb can drive and observe the existing packetizer RTL through standard AXI Stream ports without embedding stimulus in VHDL: - AxiStreamBytePackerWrapper - AxiStreamPacketizerWrapper / AxiStreamDepacketizerWrapper - AxiStreamPacketizer2Wrapper / AxiStreamDepacketizer2Wrapper - AxiStreamPacketizer2LoopbackWrapper (end-to-end packetize/depacketize topology)
Add thin AXI Stream / AXI-Lite wrappers so cocotb can drive and observe the existing batcher RTL through flattened interfaces: - AxiStreamBatcherWrapper - AxiStreamBatcherAxilWrapper (common + independent AXI-Lite clock modes) - AxiStreamBatcherEventBuilderWrapper (adds TDEST route mode)
Directed cocotb tests for the AXI Stream batcher family: - batch formatting, frame boundaries, sequence/count, payload preservation - ready/valid and output frame checking on the core batcher path - AXI-Lite register access and control/status behavior - event-builder routing/formatting through the wrapper topology - common-clock and asynchronous-clock configurations
Python cocotb tests and shared helpers under tests/protocols/packetizer/ covering byte-width packing, packetizer/depacketizer payload round trips, packetizer2/depacketizer2 framing, CRC and EOFE/error handling, link-drop behavior, sequence-number wrap, and packetizer2 loopback recovery.
Add packetizer cocotb regression coverage
Add batcher cocotb regression coverage
scompa18
approved these changes
Jun 15, 2026
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