Add RSSI protocol regression coverage and RTL fixes#1427

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Commits on May 4, 2026

Add validVec signal and error cycle tracking to CoaXPress RX lane mux tests
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rxFsmRst now flushes the RX assembly path FIFOs across RX/data domains, not just FSM/mux state. Previously the reset could restart parsing while stale overflow-era payload still drained ahead of re…
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More coaxpress test enhancements.
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CoaXPressRxLane.vhd (line 220): control ACKs now accumulate/check CRC and require EOP before pulsing cfgMaster.
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test_CoaXPressRx.py (line 128): top-level RX ACK stimulus now uses a real CRC.
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Merge branch 'srp-tests' into coaxpress-tests-2
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CoaXPressRxLane now keeps stream-data packets in explicit CRC and EOP states after the declared DSize payload words, instead of returning to idle immediately and accepting a new SOP early. The CRC …
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CoaXPressRxLane now exports rxError, and CoaXPressRx ORs all lane parser errors into the existing rxFsmError output alongside the high-speed FSM error. That means malformed packet trailers, includi…
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Add some missing protocol support.
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Update readme.
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Implemented the payload validity fix.
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Updated SlvDelayRam to document the runtime maxCount contract in the VHDL description header:
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Add more spec compliance.
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Moved the bridge magic values into CoaXPressPkg.vhd (line 37), including:
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Implemented HKP semantic handling as K-code payload parsing, not a made-up command decoder.
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