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JESD204B cocotb regression suite with RTL compliance fixes#1432

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jesd-ci-testing-pr
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JESD204B cocotb regression suite with RTL compliance fixes#1432
ruck314 wants to merge 6 commits into
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jesd-ci-testing-pr

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@ruck314 ruck314 commented Jun 5, 2026

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Description

Adds a spec-grounded cocotb regression suite for the SURF JESD204B (tests/protocols/jesd204b/), built clause-by-clause from the JESD204B spec, plus the RTL fixes the suite proved out.

Test suite (98 tests, all green)

  • Shared units: JesdLmfcGen frame/multiframe counters, scrambler round-trip against a 1+x^14+x^15 golden LFSR model, Jesd16bTo32b/Jesd32bTo16b width adapters
  • TX unit path: JesdSyncFsmTx code-group sync handshake, JesdIlasGen ILAS sequence content, JesdTxLane character replacement plus in-context ILAS/CGS
  • RX unit path: JesdSyncFsmRx sync FSM and error recovery, JesdAlignFrRepCh alignment-character replacement, JesdRxLane end-to-end ILAS capture and error handling
  • Top-level registers: JesdTxReg/JesdRxReg AXI-Lite map walks
  • E2E loopback: TX scramble → RX descramble integrity, elastic-buffer latency sweep, deterministic latency across resyncs, resync matrix

RTL fixes

  • JesdIlasGen: ILAS multiframe 2 now emits /Q/ + the 14 JESD204B Table-21 link-configuration octets + FCHK (previously missing entirely); config fields threaded through JesdTxLane/Jesd204bTx with defaulted generics — no netlist change for existing instantiations
  • JesdRxReg: 0x24 PowerDown read/write action swap corrected
  • JesdTxReg: missing rdata-zeroing in read decode added
  • Jesd204bTx: stale "untested scrambling" header warning cleared (now covered by the loopback scrambling tests)

ruck314 added 5 commits June 5, 2026 15:39
…dRxReg

The 0x24 address decode had its read and write actions swapped: the
write branch drove rdata from r.rxPowerDown while the read branch
loaded v.rxPowerDown from wdata. Swap them so AXI-Lite writes set
rxPowerDown and reads return its current value.
…eadback

The read decode never cleared v.axilReadSlave.rdata before the address
case, so bits left over from a previous read of a wider register could
leak into the readback of a narrower field. Zero rdata at the start of
every read transaction, matching the JesdRxReg decode.
… multiframe

Per JESD204B section 8.2 (Figure 50) and 8.3 (Tables 20/21), the second
ILAS multiframe must carry /Q/ (K28.4) at octet 1 followed by 14
link-configuration octets including the FCHK checksum. JesdIlasGen
previously emitted only the /R/ and /A/ frame delimiters.

- JesdIlasGen: add mfCnt/wordCnt counters and emit /Q/ plus the 14
  config octets during the second multiframe (mfCnt=1) in GT byte
  order. FCHK is the mod-256 sum of config octets 0-12.
- Add Q_CHAR_C (K28.4, 0x9C) to Jesd204bPkg.
- Thread the ILAS link-config generics (DID_G, BID_G, M_G, N_G,
  NPRIME_G, CS_G, S_G, HD_G, CF_G) through JesdTxLane and Jesd204bTx,
  and drive per-lane LID via a new lid_i port. All generics and the
  lid_i port are defaulted so existing instantiations compile
  unchanged.

The SURF RX ILA state counts multiframes and does not parse config
octets, so the added content cannot break SURF-to-SURF links.
…mments

- Jesd204bPkg: drop the unused jesdScrambler procedure (no references
  anywhere in the library; the per-lane scrambling lives in
  JesdScrCmb/descrambler logic).
- JesdSyncFsmRx: correct the comma-detect comment (the AND chain spans
  four consecutive cycles, not three) and remove the stale readBuff
  TODO note.
- Jesd204bTx: replace the 'scrambling not tested' header warning now
  that TX scrambling is exercised end-to-end by the cocotb loopback
  bench.
…s plumbing

Add a cocotb-based regression suite for the JESD204B library under
tests/protocols/jesd204b:

- jesd204b_test_utils.py: golden models (LFSR scrambler, LMFC, ILAS
  timeline builders) and shared testbench helpers
- Unit benches: JesdLmfcGen, JesdScramblerWrapper, Jesd16bTo32b,
  Jesd32bTo16b, JesdSyncFsmTx, JesdIlasGen, JesdTxLane, JesdSyncFsmRx,
  JesdAlignFrRepCh, JesdRxLane
- Register benches: JesdTxReg and JesdRxReg full map walks
- test_Jesd204bLoopback: end-to-end TX-to-RX loopback across parameter
  cases with golden scrambler cross-checks
- README with the coverage model and bench-to-module map

Add cocotb-facing wrappers under protocols/jesd204b/wrappers that
flatten record ports and expose AXI-Lite/GT interfaces for simulation
(JesdTxLaneWrapper, JesdRxLaneWrapper, JesdScramblerWrapper,
Jesd204bTxWrapper, Jesd204bRxWrapper, Jesd204bLoopbackWrapper), and
load them from ruckus.tcl.
@ruck314 ruck314 force-pushed the jesd-ci-testing-pr branch from 175be01 to 9c873b0 Compare June 5, 2026 22:40
@ruck314

ruck314 commented Jun 5, 2026

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Status: Released a FW build using this SURF PR to SMURF to HW regression test and validate these changes still work for their system before opening up this PR for review

@ruck314

ruck314 commented Jun 17, 2026

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Shawn confirmed that JESD still working after using a new FW build that uses this SURF branch. I think we are ready for PR reviewing now:

FPGA image build information:
===================================
BuildStamp       : MicrowaveMuxBpEthGen2: Vivado v2020.2, rdsrv403 (Ubuntu 22.04.5 LTS), Built Fri Jun 5 04:42:07 PM PDT 2026 by ruckman
FPGA Version      : 0x2050000
Git hash        : 0x30e2e6802fa3036f998f9ff8e94489ac4f3770f7

Running without GUI...
Running. Hit cntrl-c or send SIGTERM to 183 to exit.
Setting defaults from file /tmp/fw/smurf_cfg/defaults/defaults_c03_lb_lb.yml (try number 0)
AppTop.Init(): Link Not Locked: AMCc.FpgaTopLevel.AppTop.AppTopJesd[0].JesdTx.DataValid = 0 
AppTop.Init(): Link Not Locked: AMCc.FpgaTopLevel.AppTop.AppTopJesd[1].JesdTx.DataValid = 0 
AppTop.Init(): Link Not Locked: AMCc.FpgaTopLevel.AppTop.AppTopJesd[0].JesdRx.DataValid = 0 
AppTop.Init(): Link Not Locked: AMCc.FpgaTopLevel.AppTop.AppTopJesd[1].JesdRx.DataValid = 0 
AMCc.FpgaTopLevel.AppTop.writeBlocks()
AMCc.FpgaTopLevel.AppTop.AppCore.MicrowaveMuxCore[0].writeBlocks()
AMCc.FpgaTopLevel.AppTop.AppCore.MicrowaveMuxCore[1].writeBlocks()
AMCc.FpgaTopLevel.AppTop.Init()
Defaults were set correctly!
Check elastic buffers (try number 0)...
 OK - JesdRx[0].ElBuffLatency[0] = 14
 OK - JesdRx[0].ElBuffLatency[1] = 14
 OK - JesdRx[0].ElBuffLatency[2] = 255
 OK - JesdRx[0].ElBuffLatency[3] = 255
 OK - JesdRx[0].ElBuffLatency[4] = 13
 OK - JesdRx[0].ElBuffLatency[5] = 14
 OK - JesdRx[0].ElBuffLatency[6] = 14
 OK - JesdRx[0].ElBuffLatency[7] = 14
 OK - JesdRx[0].ElBuffLatency[8] = 14
 OK - JesdRx[0].ElBuffLatency[9] = 14
 OK - JesdRx[1].ElBuffLatency[0] = 13
 OK - JesdRx[1].ElBuffLatency[1] = 13
 OK - JesdRx[1].ElBuffLatency[2] = 255
 OK - JesdRx[1].ElBuffLatency[3] = 255
 OK - JesdRx[1].ElBuffLatency[4] = 14
 OK - JesdRx[1].ElBuffLatency[5] = 14
 OK - JesdRx[1].ElBuffLatency[6] = 13
 OK - JesdRx[1].ElBuffLatency[7] = 13
 OK - JesdRx[1].ElBuffLatency[8] = 13
 OK - JesdRx[1].ElBuffLatency[9] = 13
Elastic buffer check passed!

@ruck314 ruck314 marked this pull request as ready for review June 17, 2026 15:29
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