H743mini v1.13.3 - #385
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Correct typos in include/nuttx/arch.h and suppress "'noreturn' function does return" warning coming from arm_pthread_exit.c Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.
Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.
Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.
…bligatory for uart.
This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source. This produced a 430 nS glich on a F4 @168 Mhz. It was a enough to corrupt an I2C device with a bus monitor.
This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source.
This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source.
The stm32_gpiosetevent calls stm32_configgpio. So the pin is infact restored to the SDMMC/SDIO D0. The seconday init, dropped interrupts in a debug build with HW stack checking on after the GPIO glich fixes and that was how it was detected.
can_poll() would indicate that there is no space in the TX FIFO if there is already one element in the FIFO. Co-authored-by: Kenneth Thompson <ken@flyvoly.com>
…Y_RESET When NuttX is booted from a foreign (non NuttX) bootloader. There as a possibility that the bootloader configured the MPU, in an incompatible way for the NuttX memory usage. The option to reset the MPU before it is initialized may not succeed if the bss and data initialization code violated the previous MPU configurations. Added herein are ARM_MPU_RESET and ARM_MPU_EARLY_RESET. The former can be used If the system is capable of booting and running NuttX MPU configuration code without an MPU violation. The latter is used if the system can not run the bss and data initialization code. These are options so that a NuttX may be configured to not clobber a bootloader MPU configuration in a system that is architected to share the MPU configuration task.
With CONFIG_ARMV7M_DCACHE the cache maintenance operation are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is on then buffering operations are no-ops. This change enables MPU_RASR_C and MPU_RASR_B if CONFIG_ARMV7M_DCACHE is only set. if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only MPU_RASR_C is enabled. N.B When caching is disalbed unaligned access may cause hard faults so add -mno-unaligned-access It is always safe to enable Buffering in FLASH to achive unaligned access leniency, as it is not written to.
Strongly-Ordered requires aligned access unless caching is enabled. Normal memory Accesses to normal memory region are idempotent... - unaligned accesses can be supported
Allow using these functions also outside sched, where systick related calculations are performed Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…n in work_process This fixes busylooping in work_usrthread, due to incorrect time spec given to sem_timedwait _SEM_TIMEDWAIT works on absolute time stamps, using CLOCK_REALTIME Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…IGHT Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
After reviewing the data sheet for MB85RS256B, CY15B104Q, and FM25V0x the status register definitions in the driver were wrong as was the use.
…write For FAT the same buffer is used for read and writes, there is a possibility a cache line is dirty. But the fs is not dirty and will not write the sector to disk. This can be seen PX4#175 When the system is busy that cache line can be evicted after the RX DMA has completed and overwrite the data in memory. The solution is to invalidate before the DMA to prevent an evection causing an overwite, and after the DMA it to insure coherency.
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
Implementation was incomplete. This can now be used to pass the lincodeing information to a real serial port.
commit 328374f4658d11655f268f968f4c6c7a3942f320 changed the wait to use usleep. This killed the write performace from the published values in the datasheet of ~100 us to 2 mS per 256 bits. On a 1000 per tick config. It can be 10 X worse on the default 100 per tick config. This changes uses up_udelay.
master:
With CONFIG_PRIORITY_INHERITANCE set
Three tasks (name:priority) A:200, B:210, C:220
A takes semaphore. A:200
B waits semaphore. A:210
C waits semaphore A:220
A posts semaphore A:210 <- it is removed as a holder and
C takes semaphore A:210 not resotred.
C posts semaphore A:210
B takes semaphore A:210
B posts semaphore A:210
The solution is to look if the thread holds more then the
current semaphore S1 being posted. Then if the S1 holder is null
(holder array) or the holder has no more counts (linked list)
the posting thread's priority is restored to is base priority
and the pend_reprios is rest.
If the thread does hold another semaphore S2, the the pend_reprios
highest prority is used. When S2 is posted by the thread it will
be restorted to it's base priority.
sem_holder:TCB needs to track number of sems held
Priority restoration requiers to keep track of the
number of unique semaphores that are held by a task.
This will be used to determine if the removal
of the holder should revert to the base priority or
from the pend_reprios array.
A barrier should not participate in priority inheritance. This fixes the debug assertion failure on the destroy_holder called off of pthread_barrier_destroy.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
…it boundries
The IDMA needs to have 32 bit word alignment, in fact it will
AND off the lower 2 bits of the value stored in IDMABASE0R.
This bug was masked by CONFIG_ARMV7M_DCACHE causing proper word alignment
and also FAT_DMAMEMORY being aligned.
This commit extends the unaligned logic (used for dcache) to take into account
the need for a buffer copy when the buffer is ot 32 bit word.
It leverages the fact that when CONFIG_ARMV7M_DCACHE is not defined the up_xxxxx_dcache are nops.
…ot Hang system.
mmcsd_removed will be called if the card is in invalid state.
This can happen if the card is bad, or vibrations causes a power
loss.
mmcsd_removed resets:
priv->capacity = 0; /* Capacity=0 sometimes means no media */
priv->blocksize = 0;
priv->probed = false;
priv->mediachanged = false;
priv->wrbusy = false;
priv->type = MMCSD_CARDTYPE_UNKNOWN;
priv->rca = 0;
priv->selblocklen = 0;
priv->widebus = false;
If blocksize is set to 0 will cause the log2 to result
in an infinate loop in some drivers.
IS_EMPTY will check for priv->type = MMCSD_CARDTYPE_UNKNOWN
and return ENODEV.
commit miss named upstream as: idle: remove heap & stack check in idle thread see PR apache/nuttx#5266 Signed-off-by: ligd <liguiding1@xiaomi.com>
1. stm32_qspi:
- qspi_waitstatusflags() 添加超时机制，防止死循环
- qspi_command() 修复：将 ccrconfig 移至数据路径中，
无数据命令正确等待传输完成和忙标志清除
- qspi_memory() 移除冗余的等待调用，已下沉到收发函数中
- 修复 32 位值的格式化说明符
2. w25qxxxjv:
- write_enable/write_disable 轮询添加 nxsig_usleep 延迟，
降低 CPU 空转
- erase_sector 忙等待添加 nxsig_usleep 延迟
- 修复地址格式化说明符
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Summary
Impact
Testing