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library/util_pack: Use m_axis_ready to reset accum #2118

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library/util_pack: Use m_axis_ready to reset accum #2118

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5 changes: 5 additions & 0 deletions library/util_pack/util_cpack2/util_cpack2_impl.v
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,7 @@ module util_cpack2_impl #(

// Control signals from the pack shell.
wire ce;
wire flush;
wire ready;
wire reset_data;

Expand Down Expand Up @@ -112,6 +113,9 @@ module util_cpack2_impl #(

assign ce = data_wr_en & out_ready_int;

// Downstream backpressure.
assign flush = ~out_ready_int;

/*
* The cpack core itself has no backpressure. Overflows can only happen
* downstream.
Expand Down Expand Up @@ -146,6 +150,7 @@ module util_cpack2_impl #(

.enable (enable),
.ce (ce),
.flush (flush),
.ready (ready),
.in_data (interleaved_data),
.out_data (out_data),
Expand Down
7 changes: 6 additions & 1 deletion library/util_pack/util_pack_common/pack_shell.v
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Expand Up @@ -50,6 +50,7 @@ module pack_shell #(
input [NUM_OF_CHANNELS-1:0] enable,

input ce,
input flush,

output reg ready = 1'b0,
input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] in_data,
Expand Down Expand Up @@ -427,7 +428,11 @@ module pack_shell #(
* residual data. I.e. when ready is asserted rotate is 0.
*/
{ready,rotate} <= rotate + enable_count + 1'b1;
end else begin
end else if (flush == 1'b1) begin
/*
* Downstream backpressure: discard any partial accumulation so the
* next enabled window starts on a clean word boundary.
*/
ready <= 1'b0;
rotate <= 'h0;
end
Expand Down
3 changes: 2 additions & 1 deletion library/util_pack/util_upack2/util_upack2_impl.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2018-2023, 2025-2026 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -103,6 +103,7 @@ module util_upack2_impl #(

.enable (enable),
.ce (ce),
.flush (1'b0),
.ready (ready),
.in_data (s_axis_data),
.out_data (out_data),
Expand Down
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