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fix(agc): apply RADV's HTILE depth fast clears to the host depth surface - #2229
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Native Windows run, since no Windows results were posted. Setup: Windows 10 (19045), RTX 3060 Laptop (NVIDIA 616.92), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release. Head
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Please rebase; it conflicts with main in |
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Other open pull requests touch the same code. Merging one will break the other, or both implement the same thing. If this one builds on them, list them in Depends on.
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RADV clears depth by rewriting HTILE with its clear_htile_mask kernel (ZMASK to 0) instead of writing depth memory. Recognize that kernel and clear the matching host depth surface to DB_DEPTH_CLEAR when it is next bound; the depth target now records its HTILE address. AI-assisted (Claude Code). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude <noreply@anthropic.com>
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Checked on Linux (RADV host) on the rebased head: scoped build + ctest of libSceAgcDriver green, Added by us on top of your rebase:
Merging once CI is green. |
Rebased onto main as one commit (the six commits of boykopovar#374). A uniform fill over a depth surface's whole HTILE (DMA_DATA, the fill kernels or a CPU store) clears the depth and stencil aspects its ZMask and SMem fields say, to DB_DEPTH_CLEAR / DB_STENCIL_CLEAR, when the surface is next bound or sampled. Main's RADV clear_htile_mask recognition (boykopovar#2229) now goes through the same pending clear: an HTILE clear marks the matching surfaces' depth aspect, and one for a surface not created yet is applied when it is first bound. Main's HTILE address decode and this one are merged into one (TILE_SURFACE_ENABLE, a nonzero DB_HTILE_DATA_BASE and a depth format). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
…epth-clear fix(agc): apply RADV's HTILE depth fast clears to the host depth surface
Rebased onto main as one commit (the six commits of boykopovar#374). A uniform fill over a depth surface's whole HTILE (DMA_DATA, the fill kernels or a CPU store) clears the depth and stencil aspects its ZMask and SMem fields say, to DB_DEPTH_CLEAR / DB_STENCIL_CLEAR, when the surface is next bound or sampled. Main's RADV clear_htile_mask recognition (boykopovar#2229) now goes through the same pending clear: an HTILE clear marks the matching surfaces' depth aspect, and one for a surface not created yet is applied when it is first bound. Main's HTILE address decode and this one are merged into one (TILE_SURFACE_ENABLE, a nonzero DB_HTILE_DATA_BASE and a depth format). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Rebased onto main as one commit (the six commits of boykopovar#374). A uniform fill over a depth surface's whole HTILE (DMA_DATA, the fill kernels or a CPU store) clears the depth and stencil aspects its ZMask and SMem fields say, to DB_DEPTH_CLEAR / DB_STENCIL_CLEAR, when the surface is next bound or sampled. Main's RADV clear_htile_mask recognition (boykopovar#2229) now goes through the same pending clear: an HTILE clear marks the matching surfaces' depth aspect, and one for a surface not created yet is applied when it is first bound. Main's HTILE address decode and this one are merged into one (TILE_SURFACE_ENABLE, a nonzero DB_HTILE_DATA_BASE and a depth format). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Rebased onto main as one commit (the six commits of boykopovar#374). A uniform fill over a depth surface's whole HTILE (DMA_DATA, the fill kernels or a CPU store) clears the depth and stencil aspects its ZMask and SMem fields say, to DB_DEPTH_CLEAR / DB_STENCIL_CLEAR, when the surface is next bound or sampled. Main's RADV clear_htile_mask recognition (boykopovar#2229) now goes through the same pending clear: an HTILE clear marks the matching surfaces' depth aspect, and one for a surface not created yet is applied when it is first bound. Main's HTILE address decode and this one are merged into one (TILE_SURFACE_ENABLE, a nonzero DB_HTILE_DATA_BASE and a depth format). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
What
A depth surface is a host image that AnyPS5 clears once, when it creates the image, to the DB_DEPTH_CLEAR value it sees then. RADV (and real hardware) clears depth differently: it doesn't touch the depth memory, it rewrites the HTILE metadata so every tile reads as "cleared" (ZMASK = 0), and the DB returns DB_DEPTH_CLEAR for those tiles. AnyPS5 doesn't model HTILE, so after the first frame the host depth image is never cleared again.
vkQuake (PPSA99010, the homebrew Vulkan port, through RADV) shows this as a black 3D view. It uses reverse Z (GREATER_OR_EQUAL, clear to 0.0), so the depth buffer keeps the largest depth of every earlier frame, and once the camera moves nearly every world draw fails the depth test. The HUD, the 2D draws and the post-process pass are unaffected.
DepthTargetcarries the surface's HTILE address (DB_HTILE_DATA_BASE / _HI) when DB_Z_INFO.TILE_SURFACE_ENABLE is set and the base register has been written. 0x005 and 0x01e are added toDrawKeyRegisters.clear_htile_maskcompute kernel (17 GFX10 words:htile = (htile & user[5]) | user[4]over the buffer at user[2..3]).HtileDepthClearAddressrecognizes it by its code and 64x1x1 groups, and returns the HTILE address when the update leaves ZMASK at 0. The dispatch still runs, so guest memory is unchanged.DepthSurfaceViewclears the depth aspect of that surface to the draw's DB_DEPTH_CLEAR the next time the surface is bound, throughRecorder::Commands()(which ends any open render pass) with barriers around the clear.HTILE initialization (ZMASK 0xf, "expanded") and the stencil-only update RADV issues alongside it are left alone.
Limits: this matches one RADV kernel. Fast clears done some other way (the SDK's own paths, CP DMA fills, stencil HTILE clears) aren't covered.
Tests:
DepthStencilTests: the HTILE address decodes from DB_HTILE_DATA_BASE and its high byte, is 0 without the base register or without TILE_SURFACE_ENABLE, and every register the decoder reads is inDrawKeyRegisters.htileDepthClearTests: the fast clear is recognized; HTILE initialization, the ZMASK-preserving stencil update, another group size, a changed kernel and a truncated kernel are not.Other open PRs touch the same files (#1684, #2076, #2169 in DepthSurface/State, #2095 in the Graphics tests); I'll rebase onto whichever lands first.
Tested
Windows 11 Pro (26200), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release, NVIDIA GeForce RTX 5070 Ti (driver 610.88).
guest_sce_nettimed out (also when run alone; it doesn't touch the AGC driver, likely my local network filtering). It was run from the generatedCTestTestfile.cmakecommands because antivirus blocksctest.exeon this machine.tools/check_conventions.py --base origin/mainpasses.mainplus my open RADV PRs and some local stubs), so it isn't reproducible onmainalone.Not tested on Linux or macOS.
Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt.mdfiles or images added to the repository (attach them to this PR)🤖 Generated with Claude Code