Fix ASID extraction causing TLB flush and update PS submodule to latest

[esmakokten]

Summary of this Pull Request (PR)

Stops the TLB flush on every synchronous invocation.

chal_pgtbl_update() passed an already-extracted ASID to chal_cached_pt_curr() / chal_cached_pt_update(), which applied PROTDOM_ASID() to it again. Every ASID below 16 collapsed onto slot 0 of tlb_asid_map, so the cached-pgtbl check missed on every component crossing and CR3_NO_FLUSH was never set: each sinv and sret flushed the TLB entries of the PCID being loaded. The helpers now take the ASID directly, and tlb_asid_map gets the slot for ASID NUM_ASID_MAX, which the collapse was masking.

pong_call round trip on bare metal (Xeon Platinum 8160, min of 64 × 1024-call samples): 1127 → 851 cycles with ping_pong.toml, 1152 → 851 with sched_ping_pong.toml.

For reviewers: nothing relied on the extra flushes for memory reuse. chal_flush_tlb() is empty on x86_64, and the quiescence checks gating retype, remap and kmem release fail closed. Revocation by unmap is weaker, though: an unmapped page's stale translation now survives on the local core until that ASID's cached page table changes. It was never enforced on remote cores (chal_remote_tlb_flush() is empty).

Intent for your PR

Choose one (Mandatory):

• This PR is for a code-review and is intended to get feedback, but not to be pulled yet.
• This PR is mature, and ready to be integrated into the repo.

Reviewers (Mandatory):

@gparmer

Code Quality

As part of this pull request, I've considered the following:

Style:

• Comments adhere to the Style Guide (SG)
• Spacing adhere's to the SG
• Naming adhere's to the SG
• All other aspects of the SG are adhered to, or exceptions are justified in this pull request
• I have run the auto formatter on my code before submitting this PR (see doc/auto_formatter.md for instructions)

Code Craftsmanship:

• I've made an attempt to remove all redundant code
• I've considered ways in which my changes might impact existing code, and cleaned it up
• I've formatted the code in an effort to make it easier to read (proper error handling, function use, etc...)
• I've commented appropriately where code is tricky
• I agree that there is no "throw-away" code, and that code in this PR is of high quality

Testing

I've tested the code using the following test programs (provide list here):

• micro_booter (no longer in the tree)
• unit_schedcomp: sched_ping_pong.toml, QEMU and bare metal

[Copilot]

🟡 Changes recommended

TLB invalidation must be addressed to prevent stale translations and access violations.

Get a fresh assessment by requesting another Copilot review.

Pull request overview

Fixes x86 ASID caching to avoid unnecessary TLB flushes and cover the full ASID range.

Changes:

• Passes extracted ASIDs directly to cache helpers.
• Expands the ASID map to include the maximum ASID.
• Critical issue: mapping changes lack required TLB invalidation before CR3_NO_FLUSH reuse.

File summaries

File	Summary
src/platform/i386/chal/chal_proto.h	Corrects ASID cache indexing and sizing; requires invalidation handling for modified mappings.

Review details

• Files reviewed: 2/2 changed files
• Comments generated: 1
• Review effort level: Lite

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