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Fix ASID extraction causing TLB flush and update PS submodule to latest #503

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Fix ASID extraction causing TLB flush and update PS submodule to latest #503

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efdef3a
chal: extract the ASID once so CR3_NO_FLUSH takes effect
esmakokten Sep 11, 2026
4e069fe
ps: update submodule to gwsystems/ps master
esmakokten Sep 11, 2026
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2 changes: 1 addition & 1 deletion src/components/lib/ps/ps
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Submodule ps updated 4 files
+2 −0 plat/arch/armv7a/ps_arch_armv7a_common.h
+2 −0 plat/arch/x86/ps_arch_x86_common.h
+3 −5 ps_list.h
+58 −0 tests/list_example.c
18 changes: 13 additions & 5 deletions src/platform/i386/chal/chal_proto.h
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Original file line number Diff line number Diff line change
Expand Up @@ -146,23 +146,31 @@ chal_protdom_read(void)
#endif /* MPK_ENABLED */


/*
* Indexed by ASID, so it needs a slot for every representable name:
* PROTDOM_ASID() yields 0..NUM_ASID_MAX inclusive.
*/
struct cpu_tlb_asid_map {
pgtbl_t mapped_pt[NUM_ASID_MAX];
pgtbl_t mapped_pt[NUM_ASID_MAX + 1];
} CACHE_ALIGNED;

extern struct cpu_tlb_asid_map tlb_asid_map[NUM_CPU];

/*
* These take an ASID, not a prot_domain_t: the caller has already
* extracted it. Applying PROTDOM_ASID() again here collapsed every
* ASID < 16 onto slot 0, so the cached-pgtbl check missed on every
* component crossing and CR3_NO_FLUSH was never set.
*/
static inline pgtbl_t
chal_cached_pt_curr(prot_domain_t protdom)
chal_cached_pt_curr(u16_t asid)
{
u16_t asid = PROTDOM_ASID(protdom);
return tlb_asid_map[get_cpuid()].mapped_pt[asid];
}

static inline void
chal_cached_pt_update(pgtbl_t pt, prot_domain_t protdom)
chal_cached_pt_update(pgtbl_t pt, u16_t asid)
{
u16_t asid = PROTDOM_ASID(protdom);
tlb_asid_map[get_cpuid()].mapped_pt[asid] = pt;
}

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