Cortex-M: add opt-in explicit layout lowering - #21967
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21967
Note: Links to docs will display an error until the docs builds have been completed. ❌ 1 New Failure, 9 Unrelated Failures, 1 Unclassified FailureAs of commit 83ec2a7 with merge base 8b93850 ( NEW FAILURE - The following job has failed:
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BROKEN TRUNK - The following jobs failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This was referenced Aug 20, 2026
This was referenced Aug 21, 2026
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Thread an experimental explicit-layout mode through the shared Edge compile
configuration, AOT compiler, quantizer, tester, and pass manager while retaining
legacy dim-order export as the default.
Explicit mode disables dim-order operators, converts Conv1d through the common
transform, runs the common channels-last pipeline, lowers anchors to the fixed
_nhwc schemas, and lowers surviving boundaries to cortex_m transpose. Output
dequantization remains a layout barrier, and unequal-shape add or multiply stays
outside the region until separately admitted.
Remove identity clones once qparams are folded, so explicit mode does not need a
second clone operator in the selective build. The pass has to run after folding:
removing clones first changes the quantize topology the fold matches and splits
the layout region in two.
Package the host test harness and assert expected Cortex-M targets before
planned-memory comparisons.
Local Corstone-300 run of the full Cortex-M suite, the common-transform suites,
and lintrunner. Not run on Cortex-M33.
Authored with Codex.